leda.fit.qmsg

VHDL流水灯程序

{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0 0 "Fitter placement operations beginning" 0 0 "" 0 -1}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0 0 "Fitter placement was successful" 0 0 "" 0 -1}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:01 " "Info: Fitter placement operations ending: elapsed time is 00:00:01" {  } {  } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "" 0 -1}
{ "Info" "ITDB_FULL_SLACK_TPD_RESULT" "register \\P1:count\[7\] register \\P1:count\[22\] -7.374 ns " "Info: Slack time is -7.374 ns between source register \"\\P1:count\[7\]\" and destination register \"\\P1:count\[22\]\"" { { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "0.736 ns + Largest register register " "Info: + Largest register to register requirement is 0.736 ns" {  } {  } 0 0 "%2!c! %3!s! %4!s! to %5!s! requirement is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.545 ns   Shortest register " "Info:   Shortest clock path from clock \"clk\" to destination register is 2.545 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.854 ns) 0.854 ns clk 1 CLK Unassigned 2 " "Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = Unassigned; Fanout = 2; CLK Node = 'clk'" {  } { { "d:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "LEDA.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/LED流水灯A/LEDA.vhd" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.138 ns) + CELL(0.000 ns) 0.992 ns clk~clkctrl 2 COMB Unassigned 24 " "Info: 2: + IC(0.138 ns) + CELL(0.000 ns) = 0.992 ns; Loc. = Unassigned; Fanout = 24; COMB Node = 'clk~clkctrl'" {  } { { "d:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/bin/TimingClosureFloorplan.fld" "" "0.138 ns" { clk clk~clkctrl } "NODE_NAME" } } { "LEDA.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/LED流水灯A/LEDA.vhd" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.887 ns) + CELL(0.666 ns) 2.545 ns \\P1:count\[22\] 3 REG Unassigned 4 " "Info: 3: + IC(0.887 ns) + CELL(0.666 ns) = 2.545 ns; Loc. = Unassigned; Fanout = 4; REG Node = '\\P1:count\[22\]'" {  } { { "d:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/bin/TimingClosureFloorplan.fld" "" "1.553 ns" { clk~clkctrl \P1:count[22] } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.520 ns ( 59.72 % ) " "Info: Total cell delay = 1.520 ns ( 59.72 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "1.025 ns ( 40.28 % ) " "Info: Total interconnect delay = 1.025 ns ( 40.28 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "LEDA.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/LED流水灯A/LEDA.vhd" 11 -1 0 } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.545 ns   Longest register " "Info:   Longest clock path from clock \"clk\" to destination register is 2.545 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.854 ns) 0.854 ns clk 1 CLK Unassigned 2 " "Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = Unassigned; Fanout = 2; CLK Node = 'clk'" {  } { { "d:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "LEDA.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/LED流水灯A/LEDA.vhd" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.138 ns) + CELL(0.000 ns) 0.992 ns clk~clkctrl 2 COMB Unassigned 24 " "Info: 2: + IC(0.138 ns) + CELL(0.000 ns) = 0.992 ns; Loc. = Unassigned; Fanout = 24; COMB Node = 'clk~clkctrl'" {  } { { "d:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/bin/TimingClosureFloorplan.fld" "" "0.138 ns" { clk clk~clkctrl } "NODE_NAME" } } { "LEDA.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/LED流水灯A/LEDA.vhd" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.887 ns) + CELL(0.666 ns) 2.545 ns \\P1:count\[22\] 3 REG Unassigned 4 " "Info: 3: + IC(0.887 ns) + CELL(0.666 ns) = 2.545 ns; Loc. = Unassigned; Fanout = 4; REG Node = '\\P1:count\[22\]'" {  } { { "d:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/bin/TimingClosureFloorplan.fld" "" "1.553 ns" { clk~clkctrl \P1:count[22] } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.520 ns ( 59.72 % ) " "Info: Total cell delay = 1.520 ns ( 59.72 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "1.025 ns ( 40.28 % ) " "Info: Total interconnect delay = 1.025 ns ( 40.28 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "LEDA.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/LED流水灯A/LEDA.vhd" 11 -1 0 } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.545 ns   Shortest register " "Info:   Shortest clock path from clock \"clk\" to source register is 2.545 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.854 ns) 0.854 ns clk 1 CLK Unassigned 2 " "Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = Unassigned; Fanout = 2; CLK Node = 'clk'" {  } { { "d:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "LEDA.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/LED流水灯A/LEDA.vhd" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.138 ns) + CELL(0.000 ns) 0.992 ns clk~clkctrl 2 COMB Unassigned 24 " "Info: 2: + IC(0.138 ns) + CELL(0.000 ns) = 0.992 ns; Loc. = Unassigned; Fanout = 24; COMB Node = 'clk~clkctrl'" {  } { { "d:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/bin/TimingClosureFloorplan.fld" "" "0.138 ns" { clk clk~clkctrl } "NODE_NAME" } } { "LEDA.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/LED流水灯A/LEDA.vhd" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.887 ns) + CELL(0.666 ns) 2.545 ns \\P1:count\[7\] 3 REG Unassigned 5 " "Info: 3: + IC(0.887 ns) + CELL(0.666 ns) = 2.545 ns; Loc. = Unassigned; Fanout = 5; REG Node = '\\P1:count\[7\]'" {  } { { "d:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/bin/TimingClosureFloorplan.fld" "" "1.553 ns" { clk~clkctrl \P1:count[7] } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.520 ns ( 59.72 % ) " "Info: Total cell delay = 1.520 ns ( 59.72 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "1.025 ns ( 40.28 % ) " "Info: Total interconnect delay = 1.025 ns ( 40.28 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "LEDA.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/LED流水灯A/LEDA.vhd" 11 -1 0 } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.545 ns   Longest register " "Info:   Longest clock path from clock \"clk\" to source register is 2.545 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.854 ns) 0.854 ns clk 1 CLK Unassigned 2 " "Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = Unassigned; Fanout = 2; CLK Node = 'clk'" {  } { { "d:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "LEDA.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/LED流水灯A/LEDA.vhd" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.138 ns) + CELL(0.000 ns) 0.992 ns clk~clkctrl 2 COMB Unassigned 24 " "Info: 2: + IC(0.138 ns) + CELL(0.000 ns) = 0.992 ns; Loc. = Unassigned; Fanout = 24; COMB Node = 'clk~clkctrl'" {  } { { "d:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/bin/TimingClosureFloorplan.fld" "" "0.138 ns" { clk clk~clkctrl } "NODE_NAME" } } { "LEDA.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/LED流水灯A/LEDA.vhd" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.887 ns) + CELL(0.666 ns) 2.545 ns \\P1:count\[7\] 3 REG Unassigned 5 " "Info: 3: + IC(0.887 ns) + CELL(0.666 ns) = 2.545 ns; Loc. = Unassigned; Fanout = 5; REG Node = '\\P1:count\[7\]'" {  } { { "d:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/bin/TimingClosureFloorplan.fld" "" "1.553 ns" { clk~clkctrl \P1:count[7] } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.520 ns ( 59.72 % ) " "Info: Total cell delay = 1.520 ns ( 59.72 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "1.025 ns ( 40.28 % ) " "Info: Total interconnect delay = 1.025 ns ( 40.28 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "LEDA.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/LED流水灯A/LEDA.vhd" 11 -1 0 } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns   " "Info:   Micro clock to output delay of source is 0.304 ns" {  } {  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns   " "Info:   Micro setup delay of destination is -0.040 ns" {  } {  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.110 ns - Longest register register " "Info: - Longest register to register delay is 8.110 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns \\P1:count\[7\] 1 REG Unassigned 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = Unassigned; Fanout = 5; REG Node = '\\P1:count\[7\]'" {  } { { "d:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/bin/TimingClosureFloorplan.fld" "" "" { \P1:count[7] } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.675 ns) + CELL(0.206 ns) 0.881 ns LessThan0~0 2 COMB Unassigned 1 " "Info: 2: + IC(0.675 ns) + CELL(0.206 ns) = 0.881 ns; Loc. = Unassigned; Fanout = 1; COMB Node = 'LessThan0~0'" {  } { { "d:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/bin/TimingClosureFloorplan.fld" "" "0.881 ns" { \P1:count[7] LessThan0~0 } "NODE_NAME" } } { "LEDA.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/LED流水灯A/LEDA.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.158 ns) + CELL(0.370 ns) 2.409 ns LessThan0~1 3 COMB Unassigned 1 " "Info: 3: + IC(1.158 ns) + CELL(0.370 ns) = 2.409 ns; Loc. = Unassigned; Fanout = 1; COMB Node = 'LessThan0~1'" {  } { { "d:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/bin/TimingClosureFloorplan.fld" "" "1.528 ns" { LessThan0~0 LessThan0~1 } "NODE_NAME" } } { "LEDA.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/LED流水灯A/LEDA.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.441 ns) + CELL(0.370 ns) 3.220 ns LessThan0~2 4 COMB Unassigned 1 " "Info: 4: + IC(0.441 ns) + CELL(0.370 ns) = 3.220 ns; Loc. = Unassigned; Fanout = 1; COMB Node = 'LessThan0~2'" {  } { { "d:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/bin/TimingClosureFloorplan.fld" "" "0.811 ns" { LessThan0~1 LessThan0~2 } "NODE_NAME" } } { "LEDA.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/LED流水灯A/LEDA.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.605 ns) + CELL(0.206 ns) 4.031 ns LessThan0~3 5 COMB Unassigned 1 " "Info: 5: + IC(0.605 ns) + CELL(0.206 ns) = 4.031 ns; Loc. = Unassigned; Fanout = 1; COMB Node = 'LessThan0~3'" {  } { { "d:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/bin/TimingClosureFloorplan.fld" "" "0.811 ns" { LessThan0~2 LessThan0~3 } "NODE_NAME" } } { "LEDA.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/LED流水灯A/LEDA.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.322 ns) + CELL(0.206 ns) 5.559 ns LessThan0~4 6 COMB Unassigned 2 " "Info: 6: + IC(1.322 ns) + CELL(0.206 ns) = 5.559 ns; Loc. = Unassigned; Fanout = 2; COMB Node = 'LessThan0~4'" {  } { { "d:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/bin/TimingClosureFloorplan.fld" "" "1.528 ns" { LessThan0~3 LessThan0~4 } "NODE_NAME" } } { "LEDA.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/LED流水灯A/LEDA.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.187 ns) + CELL(0.624 ns) 6.370 ns \\P1:count\[23\]~2 7 COMB Unassigned 24 " "Info: 7: + IC(0.187 ns) + CELL(0.624 ns) = 6.370 ns; Loc. = Unassigned; Fanout = 24; COMB Node = '\\P1:count\[23\]~2'" {  } { { "d:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/bin/TimingClosureFloorplan.fld" "" "0.811 ns" { LessThan0~4 \P1:count[23]~2 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.080 ns) + CELL(0.660 ns) 8.110 ns \\P1:count\[22\] 8 REG Unassigned 4 " "Info: 8: + IC(1.080 ns) + CELL(0.660 ns) = 8.110 ns; Loc. = Unassigned; Fanout = 4; REG Node = '\\P1:count\[22\]'" {  } { { "d:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/bin/TimingClosureFloorplan.fld" "" "1.740 ns" { \P1:count[23]~2 \P1:count[22] } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.642 ns ( 32.58 % ) " "Info: Total cell delay = 2.642 ns ( 32.58 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "5.468 ns ( 67.42 % ) " "Info: Total interconnect delay = 5.468 ns ( 67.42 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "d:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/bin/TimingClosureFloorplan.fld" "" "8.110 ns" { \P1:count[7] LessThan0~0 LessThan0~1 LessThan0~2 LessThan0~3 LessThan0~4 \P1:count[23]~2 \P1:count[22] } "NODE_NAME" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 -1}  } { { "d:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/bin/TimingClosureFloorplan.fld" "" "8.110 ns" { \P1:count[7] LessThan0~0 LessThan0~1 LessThan0~2 LessThan0~3 LessThan0~4 \P1:count[23]~2 \P1:count[22] } "NODE_NAME" } }  } 0 0 "Slack time is %5!s! between source %1!s! \"%2!s!\" and destination %3!s! \"%4!s!\"" 0 0 "" 0 -1}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "8.110 ns register register " "Info: Estimated most critical path is register to register delay of 8.110 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns \\P1:count\[7\] 1 REG LAB_X32_Y6 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X32_Y6; Fanout = 5; REG Node = '\\P1:count\[7\]'" {  } { { "d:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/bin/TimingClosureFloorplan.fld" "" "" { \P1:count[7] } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.675 ns) + CELL(0.206 ns) 0.881 ns LessThan0~0 2 COMB LAB_X32_Y6 1 " "Info: 2: + IC(0.675 ns) + CELL(0.206 ns) = 0.881 ns; Loc. = LAB_X32_Y6; Fanout = 1; COMB Node = 'LessThan0~0'" {  } { { "d:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/bin/TimingClosureFloorplan.fld" "" "0.881 ns" { \P1:count[7] LessThan0~0 } "NODE_NAME" } } { "LEDA.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/LED流水灯A/LEDA.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.158 ns) + CELL(0.370 ns) 2.409 ns LessThan0~1 3 COMB LAB_X32_Y5 1 " "Info: 3: + IC(1.158 ns) + CELL(0.370 ns) = 2.409 ns; Loc. = LAB_X32_Y5; Fanout = 1; COMB Node = 'LessThan0~1'" {  } { { "d:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/bin/TimingClosureFloorplan.fld" "" "1.528 ns" { LessThan0~0 LessThan0~1 } "NODE_NAME" } } { "LEDA.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/LED流水灯A/LEDA.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.441 ns) + CELL(0.370 ns) 3.220 ns LessThan0~2 4 COMB LAB_X32_Y5 1 " "Info: 4: + IC(0.441 ns) + CELL(0.370 ns) = 3.220 ns; Loc. = LAB_X32_Y5; Fanout = 1; COMB Node = 'LessThan0~2'" {  } { { "d:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/bin/TimingClosureFloorplan.fld" "" "0.811 ns" { LessThan0~1 LessThan0~2 } "NODE_NAME" } } { "LEDA.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/LED流水灯A/LEDA.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.605 ns) + CELL(0.206 ns) 4.031 ns LessThan0~3 5 COMB LAB_X32_Y5 1 " "Info: 5: + IC(0.605 ns) + CELL(0.206 ns) = 4.031 ns; Loc. = LAB_X32_Y5; Fanout = 1; COMB Node = 'LessThan0~3'" {  } { { "d:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/bin/TimingClosureFloorplan.fld" "" "0.811 ns" { LessThan0~2 LessThan0~3 } "NODE_NAME" } } { "LEDA.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/LED流水灯A/LEDA.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.322 ns) + CELL(0.206 ns) 5.559 ns LessThan0~4 6 COMB LAB_X32_Y6 2 " "Info: 6: + IC(1.322 ns) + CELL(0.206 ns) = 5.559 ns; Loc. = LAB_X32_Y6; Fanout = 2; COMB Node = 'LessThan0~4'" {  } { { "d:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/bin/TimingClosureFloorplan.fld" "" "1.528 ns" { LessThan0~3 LessThan0~4 } "NODE_NAME" } } { "LEDA.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/LED流水灯A/LEDA.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.187 ns) + CELL(0.624 ns) 6.370 ns \\P1:count\[23\]~2 7 COMB LAB_X32_Y6 24 " "Info: 7: + IC(0.187 ns) + CELL(0.624 ns) = 6.370 ns; Loc. = LAB_X32_Y6; Fanout = 24; COMB Node = '\\P1:count\[23\]~2'" {  } { { "d:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/bin/TimingClosureFloorplan.fld" "" "0.811 ns" { LessThan0~4 \P1:count[23]~2 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.080 ns) + CELL(0.660 ns) 8.110 ns \\P1:count\[22\] 8 REG LAB_X32_Y5 4 " "Info: 8: + IC(1.080 ns) + CELL(0.660 ns) = 8.110 ns; Loc. = LAB_X32_Y5; Fanout = 4; REG Node = '\\P1:count\[22\]'" {  } { { "d:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/bin/TimingClosureFloorplan.fld" "" "1.740 ns" { \P1:count[23]~2 \P1:count[22] } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.642 ns ( 32.58 % ) " "Info: Total cell delay = 2.642 ns ( 32.58 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "5.468 ns ( 67.42 % ) " "Info: Total interconnect delay = 5.468 ns ( 67.42 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "d:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/bin/TimingClosureFloorplan.fld" "" "8.110 ns" { \P1:count[7] LessThan0~0 LessThan0~1 LessThan0~2 LessThan0~3 LessThan0~4 \P1:count[23]~2 \P1:count[22] } "NODE_NAME" } }  } 0 0 "Estimated most critical path is %2!s! to %3!s! delay of %1!s!" 0 0 "" 0 -1}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0 0 "Fitter routing operations beginning" 0 0 "" 0 -1}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Info: Average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X23_Y0 X34_Y9 " "Info: Peak interconnect usage is 0% of the available device resources in the region that extends from location X23_Y0 to location X34_Y9" {  } {  } 0 0 "Peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "" 0 -1}  } {  } 0 0 "Average interconnect usage is %1!d!%% of the available device resources" 0 0 "" 0 -1}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Info: Fitter routing operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "" 0 -1}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Info: Optimizations that may affect the design's routability were skipped" {  } {  } 0 0 "Optimizations that may affect the design's routability were skipped" 0 0 "" 0 -1} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Info: Optimizations that may affect the design's timing were skipped" {  } {  } 0 0 "Optimizations that may affect the design's timing were skipped" 0 0 "" 0 -1}  } {  } 0 0 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0 "" 0 -1}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0 0 "Started post-fitting delay annotation" 0 0 "" 0 -1}
{ "Warning" "WDAT_NO_LOADING_SPECIFIED_ONE_OR_MORE_PINS" "8 " "Warning: Found 8 output pins without output pin load capacitance assignment" { { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "led1\[0\] 0 " "Info: Pin \"led1\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "led1\[1\] 0 " "Info: Pin \"led1\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "led1\[2\] 0 " "Info: Pin \"led1\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "led1\[3\] 0 " "Info: Pin \"led1\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "led1\[4\] 0 " "Info: Pin \"led1\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "led1\[5\] 0 " "Info: Pin \"led1\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "led1\[6\] 0 " "Info: Pin \"led1\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "led1\[7\] 0 " "Info: Pin \"led1\[7\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1}  } {  } 0 0 "Found %1!d! output pins without output pin load capacitance assignment" 0 0 "" 0 -1}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0 "" 0 -1}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 3 s Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "190 " "Info: Peak virtual memory: 190 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Fri Aug 06 19:56:47 2010 " "Info: Processing ended: Fri Aug 06 19:56:47 2010" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:11 " "Info: Elapsed time: 00:00:11" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:06 " "Info: Total CPU time (on all processors): 00:00:06" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}