prev_cmp_leda.qmsg

VHDL流水灯程序

{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Warning: Feature LogicLock is not available with your current license" {  } {  } 0 0 "Feature %1!s! is not available with your current license" 0 0 "" 0 -1}
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C5Q208C8 " "Info: Device EP2C5Q208C8 is compatible" {  } {  } 2 0 "Device %1!s! is compatible" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C5Q208I8 " "Info: Device EP2C5Q208I8 is compatible" {  } {  } 2 0 "Device %1!s! is compatible" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C8Q208I8 " "Info: Device EP2C8Q208I8 is compatible" {  } {  } 2 0 "Device %1!s! is compatible" 0 0 "" 0 -1}  } {  } 2 0 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "" 0 -1}
{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "3 " "Info: Fitter converted 3 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ASDO~ 1 " "Info: Pin ~ASDO~ is reserved at location 1" {  } { { "d:/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/quartus/bin/pin_planner.ppl" { ~ASDO~ } } } { "d:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~ASDO~ } "NODE_NAME" } }  } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0 -1} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~nCSO~ 2 " "Info: Pin ~nCSO~ is reserved at location 2" {  } { { "d:/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/quartus/bin/pin_planner.ppl" { ~nCSO~ } } } { "d:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~nCSO~ } "NODE_NAME" } }  } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0 -1} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~LVDS54p/nCEO~ 108 " "Info: Pin ~LVDS54p/nCEO~ is reserved at location 108" {  } { { "d:/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/quartus/bin/pin_planner.ppl" { ~LVDS54p/nCEO~ } } } { "d:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~LVDS54p/nCEO~ } "NODE_NAME" } }  } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "" 0 -1}
{ "Warning" "WFIOMGR_PINS_MISSING_LOCATION_INFO" "2 9 " "Warning: No exact pin location assignment(s) for 2 pins of 9 total pins" { { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "led1\[6\] " "Info: Pin led1\[6\] not assigned to an exact location on the device" {  } { { "d:/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/quartus/bin/pin_planner.ppl" { led1[6] } } } { "LEDA.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/LED流水灯A/LEDA.vhd" 41 -1 0 } } { "d:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/bin/TimingClosureFloorplan.fld" "" "" { led1[6] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "led1\[7\] " "Info: Pin led1\[7\] not assigned to an exact location on the device" {  } { { "d:/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/quartus/bin/pin_planner.ppl" { led1[7] } } } { "LEDA.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/LED流水灯A/LEDA.vhd" 41 -1 0 } } { "d:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/bin/TimingClosureFloorplan.fld" "" "" { led1[7] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1}  } {  } 0 0 "No exact pin location assignment(s) for %1!d! pins of %2!d! total pins" 0 0 "" 0 -1}
{ "Info" "ITDC_FITTER_TIMING_ENGINE" "Classic " "Info: Fitter is using the Classic Timing Analyzer" {  } {  } 0 0 "Fitter is using the %1!s! Timing Analyzer" 0 0 "" 0 -1}
{ "Info" "ITAN_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Info: Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time." {  } {  } 0 0 "Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time." 0 0 "" 0 -1}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "clk (placed in PIN 23 (CLK0, LVDSCLK0p, Input)) " "Info: Automatically promoted node clk (placed in PIN 23 (CLK0, LVDSCLK0p, Input))" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G2 " "Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G2" {  } {  } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Info: Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "clk1 " "Info: Destination node clk1" {  } { { "LEDA.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/LED流水灯A/LEDA.vhd" 15 -1 0 } } { "d:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk1 } "NODE_NAME" } }  } 0 0 "Destination node %1!s!" 0 0 "" 0 -1}  } {  } 0 0 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0 "" 0 -1}  } { { "d:/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/quartus/bin/pin_planner.ppl" { clk } } } { "d:/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } } { "LEDA.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/LED流水灯A/LEDA.vhd" 11 -1 0 } } { "d:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } }  } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0 "" 0 -1}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "CLK2  " "Info: Automatically promoted node CLK2 " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Info: Automatically promoted destinations to use location or clock signal Global Clock" {  } {  } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Info: Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "CLK2~0 " "Info: Destination node CLK2~0" {  } { { "LEDA.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/LED流水灯A/LEDA.vhd" 15 -1 0 } } { "d:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK2~0 } "NODE_NAME" } }  } 0 0 "Destination node %1!s!" 0 0 "" 0 -1}  } {  } 0 0 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0 "" 0 -1}  } { { "LEDA.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/LED流水灯A/LEDA.vhd" 15 -1 0 } } { "d:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK2 } "NODE_NAME" } }  } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0 "" 0 -1}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Info: Starting register packing" {  } {  } 0 0 "Starting register packing" 0 0 "" 0 -1}
{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Extra Info: Performing register packing on registers with non-logic cell location assignments" {  } {  } 1 0 "Performing register packing on registers with non-logic cell location assignments" 1 0 "" 0 -1}
{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Extra Info: Completed register packing on registers with non-logic cell location assignments" {  } {  } 1 0 "Completed register packing on registers with non-logic cell location assignments" 1 0 "" 0 -1}
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Extra Info: Started Fast Input/Output/OE register processing" {  } {  } 1 0 "Started Fast Input/Output/OE register processing" 1 0 "" 0 -1}
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Extra Info: Finished Fast Input/Output/OE register processing" {  } {  } 1 0 "Finished Fast Input/Output/OE register processing" 1 0 "" 0 -1}
{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Extra Info: Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" {  } {  } 1 0 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "" 0 -1}
{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Extra Info: Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" {  } {  } 1 0 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "" 0 -1}