prev_cmp_leda.tan.qmsg

VHDL流水灯程序

{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "2 " "Warning: Found 2 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "clk1 " "Info: Detected ripple clock \"clk1\" as buffer" {  } { { "LEDA.vhd" "" { Text "G:/做视频教材要用的/VHDL/LED流水灯A/LEDA.vhd" 12 -1 0 } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk1" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0 -1} { "Info" "ITAN_RIPPLE_CLK" "CLK2 " "Info: Detected ripple clock \"CLK2\" as buffer" {  } { { "LEDA.vhd" "" { Text "G:/做视频教材要用的/VHDL/LED流水灯A/LEDA.vhd" 12 -1 0 } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "CLK2" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0 -1}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0 "" 0 -1}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register \\P1:count\[11\] register \\P1:count\[19\] 186.19 MHz 5.371 ns Internal " "Info: Clock \"clk\" has Internal fmax of 186.19 MHz between source register \"\\P1:count\[11\]\" and destination register \"\\P1:count\[19\]\" (period= 5.371 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.107 ns + Longest register register " "Info: + Longest register to register delay is 5.107 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns \\P1:count\[11\] 1 REG LCFF_X12_Y9_N3 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X12_Y9_N3; Fanout = 3; REG Node = '\\P1:count\[11\]'" {  } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { \P1:count[11] } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.152 ns) + CELL(0.539 ns) 1.691 ns LessThan2~0 2 COMB LCCOMB_X12_Y10_N2 2 " "Info: 2: + IC(1.152 ns) + CELL(0.539 ns) = 1.691 ns; Loc. = LCCOMB_X12_Y10_N2; Fanout = 2; COMB Node = 'LessThan2~0'" {  } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "1.691 ns" { \P1:count[11] LessThan2~0 } "NODE_NAME" } } { "LEDA.vhd" "" { Text "G:/做视频教材要用的/VHDL/LED流水灯A/LEDA.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.371 ns) + CELL(0.206 ns) 2.268 ns count~42 3 COMB LCCOMB_X12_Y10_N6 1 " "Info: 3: + IC(0.371 ns) + CELL(0.206 ns) = 2.268 ns; Loc. = LCCOMB_X12_Y10_N6; Fanout = 1; COMB Node = 'count~42'" {  } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "0.577 ns" { LessThan2~0 count~42 } "NODE_NAME" } } { "LEDA.vhd" "" { Text "G:/做视频教材要用的/VHDL/LED流水灯A/LEDA.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.363 ns) + CELL(0.206 ns) 2.837 ns count~43 4 COMB LCCOMB_X12_Y10_N0 2 " "Info: 4: + IC(0.363 ns) + CELL(0.206 ns) = 2.837 ns; Loc. = LCCOMB_X12_Y10_N0; Fanout = 2; COMB Node = 'count~43'" {  } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "0.569 ns" { count~42 count~43 } "NODE_NAME" } } { "LEDA.vhd" "" { Text "G:/做视频教材要用的/VHDL/LED流水灯A/LEDA.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.368 ns) + CELL(0.206 ns) 3.411 ns count~44 5 COMB LCCOMB_X12_Y10_N10 20 " "Info: 5: + IC(0.368 ns) + CELL(0.206 ns) = 3.411 ns; Loc. = LCCOMB_X12_Y10_N10; Fanout = 20; COMB Node = 'count~44'" {  } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "0.574 ns" { count~43 count~44 } "NODE_NAME" } } { "LEDA.vhd" "" { Text "G:/做视频教材要用的/VHDL/LED流水灯A/LEDA.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.036 ns) + CELL(0.660 ns) 5.107 ns \\P1:count\[19\] 6 REG LCFF_X12_Y9_N19 4 " "Info: 6: + IC(1.036 ns) + CELL(0.660 ns) = 5.107 ns; Loc. = LCFF_X12_Y9_N19; Fanout = 4; REG Node = '\\P1:count\[19\]'" {  } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "1.696 ns" { count~44 \P1:count[19] } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.817 ns ( 35.58 % ) " "Info: Total cell delay = 1.817 ns ( 35.58 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "3.290 ns ( 64.42 % ) " "Info: Total interconnect delay = 3.290 ns ( 64.42 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "5.107 ns" { \P1:count[11] LessThan2~0 count~42 count~43 count~44 \P1:count[19] } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "5.107 ns" { \P1:count[11] {} LessThan2~0 {} count~42 {} count~43 {} count~44 {} \P1:count[19] {} } { 0.000ns 1.152ns 0.371ns 0.363ns 0.368ns 1.036ns } { 0.000ns 0.539ns 0.206ns 0.206ns 0.206ns 0.660ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.829 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 2.829 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns clk 1 CLK PIN_23 2 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 2; CLK Node = 'clk'" {  } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "LEDA.vhd" "" { Text "G:/做视频教材要用的/VHDL/LED流水灯A/LEDA.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.279 ns clk~clkctrl 2 COMB CLKCTRL_G2 20 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.279 ns; Loc. = CLKCTRL_G2; Fanout = 20; COMB Node = 'clk~clkctrl'" {  } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "0.139 ns" { clk clk~clkctrl } "NODE_NAME" } } { "LEDA.vhd" "" { Text "G:/做视频教材要用的/VHDL/LED流水灯A/LEDA.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.884 ns) + CELL(0.666 ns) 2.829 ns \\P1:count\[19\] 3 REG LCFF_X12_Y9_N19 4 " "Info: 3: + IC(0.884 ns) + CELL(0.666 ns) = 2.829 ns; Loc. = LCFF_X12_Y9_N19; Fanout = 4; REG Node = '\\P1:count\[19\]'" {  } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "1.550 ns" { clk~clkctrl \P1:count[19] } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.806 ns ( 63.84 % ) " "Info: Total cell delay = 1.806 ns ( 63.84 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "1.023 ns ( 36.16 % ) " "Info: Total interconnect delay = 1.023 ns ( 36.16 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "2.829 ns" { clk clk~clkctrl \P1:count[19] } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "2.829 ns" { clk {} clk~combout {} clk~clkctrl {} \P1:count[19] {} } { 0.000ns 0.000ns 0.139ns 0.884ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.829 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 2.829 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns clk 1 CLK PIN_23 2 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 2; CLK Node = 'clk'" {  } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "LEDA.vhd" "" { Text "G:/做视频教材要用的/VHDL/LED流水灯A/LEDA.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.279 ns clk~clkctrl 2 COMB CLKCTRL_G2 20 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.279 ns; Loc. = CLKCTRL_G2; Fanout = 20; COMB Node = 'clk~clkctrl'" {  } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "0.139 ns" { clk clk~clkctrl } "NODE_NAME" } } { "LEDA.vhd" "" { Text "G:/做视频教材要用的/VHDL/LED流水灯A/LEDA.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.884 ns) + CELL(0.666 ns) 2.829 ns \\P1:count\[11\] 3 REG LCFF_X12_Y9_N3 3 " "Info: 3: + IC(0.884 ns) + CELL(0.666 ns) = 2.829 ns; Loc. = LCFF_X12_Y9_N3; Fanout = 3; REG Node = '\\P1:count\[11\]'" {  } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "1.550 ns" { clk~clkctrl \P1:count[11] } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.806 ns ( 63.84 % ) " "Info: Total cell delay = 1.806 ns ( 63.84 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "1.023 ns ( 36.16 % ) " "Info: Total interconnect delay = 1.023 ns ( 36.16 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "2.829 ns" { clk clk~clkctrl \P1:count[11] } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "2.829 ns" { clk {} clk~combout {} clk~clkctrl {} \P1:count[11] {} } { 0.000ns 0.000ns 0.139ns 0.884ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1}  } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "2.829 ns" { clk clk~clkctrl \P1:count[19] } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "2.829 ns" { clk {} clk~combout {} clk~clkctrl {} \P1:count[19] {} } { 0.000ns 0.000ns 0.139ns 0.884ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "2.829 ns" { clk clk~clkctrl \P1:count[11] } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "2.829 ns" { clk {} clk~combout {} clk~clkctrl {} \P1:count[11] {} } { 0.000ns 0.000ns 0.139ns 0.884ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" {  } {  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns + " "Info: + Micro setup delay of destination is -0.040 ns" {  } {  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 -1}  } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "5.107 ns" { \P1:count[11] LessThan2~0 count~42 count~43 count~44 \P1:count[19] } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "5.107 ns" { \P1:count[11] {} LessThan2~0 {} count~42 {} count~43 {} count~44 {} \P1:count[19] {} } { 0.000ns 1.152ns 0.371ns 0.363ns 0.368ns 1.036ns } { 0.000ns 0.539ns 0.206ns 0.206ns 0.206ns 0.660ns } "" } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "2.829 ns" { clk clk~clkctrl \P1:count[19] } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "2.829 ns" { clk {} clk~combout {} clk~clkctrl {} \P1:count[19] {} } { 0.000ns 0.000ns 0.139ns 0.884ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "2.829 ns" { clk clk~clkctrl \P1:count[11] } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "2.829 ns" { clk {} clk~combout {} clk~clkctrl {} \P1:count[11] {} } { 0.000ns 0.000ns 0.139ns 0.884ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0 -1}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk led1\[7\] led1\[7\]~reg0 15.660 ns register " "Info: tco from clock \"clk\" to destination pin \"led1\[7\]\" through register \"led1\[7\]~reg0\" is 15.660 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 8.625 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 8.625 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns clk 1 CLK PIN_23 2 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 2; CLK Node = 'clk'" {  } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "LEDA.vhd" "" { Text "G:/做视频教材要用的/VHDL/LED流水灯A/LEDA.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.405 ns) + CELL(0.970 ns) 3.515 ns clk1 2 REG LCFF_X12_Y9_N25 2 " "Info: 2: + IC(1.405 ns) + CELL(0.970 ns) = 3.515 ns; Loc. = LCFF_X12_Y9_N25; Fanout = 2; REG Node = 'clk1'" {  } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "2.375 ns" { clk clk1 } "NODE_NAME" } } { "LEDA.vhd" "" { Text "G:/做视频教材要用的/VHDL/LED流水灯A/LEDA.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.407 ns) + CELL(0.970 ns) 5.892 ns CLK2 3 REG LCFF_X4_Y9_N21 2 " "Info: 3: + IC(1.407 ns) + CELL(0.970 ns) = 5.892 ns; Loc. = LCFF_X4_Y9_N21; Fanout = 2; REG Node = 'CLK2'" {  } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "2.377 ns" { clk1 CLK2 } "NODE_NAME" } } { "LEDA.vhd" "" { Text "G:/做视频教材要用的/VHDL/LED流水灯A/LEDA.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.138 ns) + CELL(0.000 ns) 7.030 ns CLK2~clkctrl 4 COMB CLKCTRL_G0 13 " "Info: 4: + IC(1.138 ns) + CELL(0.000 ns) = 7.030 ns; Loc. = CLKCTRL_G0; Fanout = 13; COMB Node = 'CLK2~clkctrl'" {  } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "1.138 ns" { CLK2 CLK2~clkctrl } "NODE_NAME" } } { "LEDA.vhd" "" { Text "G:/做视频教材要用的/VHDL/LED流水灯A/LEDA.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.929 ns) + CELL(0.666 ns) 8.625 ns led1\[7\]~reg0 5 REG LCFF_X31_Y16_N15 1 " "Info: 5: + IC(0.929 ns) + CELL(0.666 ns) = 8.625 ns; Loc. = LCFF_X31_Y16_N15; Fanout = 1; REG Node = 'led1\[7\]~reg0'" {  } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "1.595 ns" { CLK2~clkctrl led1[7]~reg0 } "NODE_NAME" } } { "LEDA.vhd" "" { Text "G:/做视频教材要用的/VHDL/LED流水灯A/LEDA.vhd" 38 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.746 ns ( 43.43 % ) " "Info: Total cell delay = 3.746 ns ( 43.43 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "4.879 ns ( 56.57 % ) " "Info: Total interconnect delay = 4.879 ns ( 56.57 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "8.625 ns" { clk clk1 CLK2 CLK2~clkctrl led1[7]~reg0 } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "8.625 ns" { clk {} clk~combout {} clk1 {} CLK2 {} CLK2~clkctrl {} led1[7]~reg0 {} } { 0.000ns 0.000ns 1.405ns 1.407ns 1.138ns 0.929ns } { 0.000ns 1.140ns 0.970ns 0.970ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" {  } { { "LEDA.vhd" "" { Text "G:/做视频教材要用的/VHDL/LED流水灯A/LEDA.vhd" 38 0 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.731 ns + Longest register pin " "Info: + Longest register to pin delay is 6.731 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns led1\[7\]~reg0 1 REG LCFF_X31_Y16_N15 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X31_Y16_N15; Fanout = 1; REG Node = 'led1\[7\]~reg0'" {  } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { led1[7]~reg0 } "NODE_NAME" } } { "LEDA.vhd" "" { Text "G:/做视频教材要用的/VHDL/LED流水灯A/LEDA.vhd" 38 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(3.635 ns) + CELL(3.096 ns) 6.731 ns led1\[7\] 2 PIN PIN_11 0 " "Info: 2: + IC(3.635 ns) + CELL(3.096 ns) = 6.731 ns; Loc. = PIN_11; Fanout = 0; PIN Node = 'led1\[7\]'" {  } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "6.731 ns" { led1[7]~reg0 led1[7] } "NODE_NAME" } } { "LEDA.vhd" "" { Text "G:/做视频教材要用的/VHDL/LED流水灯A/LEDA.vhd" 38 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.096 ns ( 46.00 % ) " "Info: Total cell delay = 3.096 ns ( 46.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "3.635 ns ( 54.00 % ) " "Info: Total interconnect delay = 3.635 ns ( 54.00 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "6.731 ns" { led1[7]~reg0 led1[7] } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "6.731 ns" { led1[7]~reg0 {} led1[7] {} } { 0.000ns 3.635ns } { 0.000ns 3.096ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 -1}  } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "8.625 ns" { clk clk1 CLK2 CLK2~clkctrl led1[7]~reg0 } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "8.625 ns" { clk {} clk~combout {} clk1 {} CLK2 {} CLK2~clkctrl {} led1[7]~reg0 {} } { 0.000ns 0.000ns 1.405ns 1.407ns 1.138ns 0.929ns } { 0.000ns 1.140ns 0.970ns 0.970ns 0.000ns 0.666ns } "" } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "6.731 ns" { led1[7]~reg0 led1[7] } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "6.731 ns" { led1[7]~reg0 {} led1[7] {} } { 0.000ns 3.635ns } { 0.000ns 3.096ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0 -1}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 2 s Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "136 " "Info: Peak virtual memory: 136 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Wed Apr 14 21:08:03 2010 " "Info: Processing ended: Wed Apr 14 21:08:03 2010" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Info: Total CPU time (on all processors): 00:00:01" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}