leda.tan.rpt

VHDL流水灯程序

+-------+--------------+------------+--------------+---------+------------+
; N/A   ; None         ; 15.480 ns  ; led1[2]~reg0 ; led1[2] ; clk        ;
; N/A   ; None         ; 15.459 ns  ; led1[3]~reg0 ; led1[3] ; clk        ;
; N/A   ; None         ; 15.153 ns  ; led1[5]~reg0 ; led1[5] ; clk        ;
; N/A   ; None         ; 15.120 ns  ; led1[4]~reg0 ; led1[4] ; clk        ;
; N/A   ; None         ; 14.589 ns  ; led1[0]~reg0 ; led1[0] ; clk        ;
; N/A   ; None         ; 14.265 ns  ; led1[6]~reg0 ; led1[6] ; clk        ;
; N/A   ; None         ; 14.173 ns  ; led1[7]~reg0 ; led1[7] ; clk        ;
; N/A   ; None         ; 14.140 ns  ; led1[1]~reg0 ; led1[1] ; clk        ;
+-------+--------------+------------+--------------+---------+------------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
    Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
    Info: Processing started: Wed Apr 14 21:14:10 2010
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off LEDA -c LEDA --timing_analysis_only
Info: Parallel compilation is enabled and will use 2 of the 2 processors detected
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Warning: Found 2 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew
    Info: Detected ripple clock "clk1" as buffer
    Info: Detected ripple clock "CLK2" as buffer
Info: Clock "clk" has Internal fmax of 130.6 MHz between source register "\P1:count[6]" and destination register "\P1:count[20]" (period= 7.657 ns)
    Info: + Longest register to register delay is 7.398 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X32_Y6_N21; Fanout = 4; REG Node = '\P1:count[6]'
        Info: 2: + IC(0.477 ns) + CELL(0.615 ns) = 1.092 ns; Loc. = LCCOMB_X32_Y6_N0; Fanout = 1; COMB Node = 'LessThan0~0'
        Info: 3: + IC(1.061 ns) + CELL(0.206 ns) = 2.359 ns; Loc. = LCCOMB_X32_Y5_N26; Fanout = 1; COMB Node = 'LessThan0~1'
        Info: 4: + IC(0.365 ns) + CELL(0.577 ns) = 3.301 ns; Loc. = LCCOMB_X32_Y5_N28; Fanout = 1; COMB Node = 'LessThan0~2'
        Info: 5: + IC(0.359 ns) + CELL(0.206 ns) = 3.866 ns; Loc. = LCCOMB_X32_Y5_N30; Fanout = 1; COMB Node = 'LessThan0~3'
        Info: 6: + IC(1.070 ns) + CELL(0.206 ns) = 5.142 ns; Loc. = LCCOMB_X32_Y6_N2; Fanout = 2; COMB Node = 'LessThan0~4'
        Info: 7: + IC(0.372 ns) + CELL(0.206 ns) = 5.720 ns; Loc. = LCCOMB_X32_Y6_N6; Fanout = 24; COMB Node = '\P1:count[23]~2'
        Info: 8: + IC(1.018 ns) + CELL(0.660 ns) = 7.398 ns; Loc. = LCFF_X32_Y5_N17; Fanout = 5; REG Node = '\P1:count[20]'
        Info: Total cell delay = 2.676 ns ( 36.17 % )
        Info: Total interconnect delay = 4.722 ns ( 63.83 % )
    Info: - Smallest clock skew is 0.005 ns
        Info: + Shortest clock path from clock "clk" to destination register is 2.867 ns
            Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 2; CLK Node = 'clk'
            Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.279 ns; Loc. = CLKCTRL_G2; Fanout = 24; COMB Node = 'clk~clkctrl'
            Info: 3: + IC(0.922 ns) + CELL(0.666 ns) = 2.867 ns; Loc. = LCFF_X32_Y5_N17; Fanout = 5; REG Node = '\P1:count[20]'
            Info: Total cell delay = 1.806 ns ( 62.99 % )
            Info: Total interconnect delay = 1.061 ns ( 37.01 % )
        Info: - Longest clock path from clock "clk" to source register is 2.862 ns
            Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 2; CLK Node = 'clk'
            Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.279 ns; Loc. = CLKCTRL_G2; Fanout = 24; COMB Node = 'clk~clkctrl'
            Info: 3: + IC(0.917 ns) + CELL(0.666 ns) = 2.862 ns; Loc. = LCFF_X32_Y6_N21; Fanout = 4; REG Node = '\P1:count[6]'
            Info: Total cell delay = 1.806 ns ( 63.10 % )
            Info: Total interconnect delay = 1.056 ns ( 36.90 % )
    Info: + Micro clock to output delay of source is 0.304 ns
    Info: + Micro setup delay of destination is -0.040 ns
Info: tco from clock "clk" to destination pin "led1[2]" through register "led1[2]~reg0" is 15.480 ns
    Info: + Longest clock path from clock "clk" to source register is 8.372 ns
        Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 2; CLK Node = 'clk'
        Info: 2: + IC(2.059 ns) + CELL(0.970 ns) = 4.169 ns; Loc. = LCFF_X33_Y6_N31; Fanout = 2; REG Node = 'clk1'
        Info: 3: + IC(0.390 ns) + CELL(0.970 ns) = 5.529 ns; Loc. = LCFF_X33_Y6_N15; Fanout = 2; REG Node = 'CLK2'
        Info: 4: + IC(1.250 ns) + CELL(0.000 ns) = 6.779 ns; Loc. = CLKCTRL_G5; Fanout = 13; COMB Node = 'CLK2~clkctrl'
        Info: 5: + IC(0.927 ns) + CELL(0.666 ns) = 8.372 ns; Loc. = LCFF_X16_Y14_N13; Fanout = 1; REG Node = 'led1[2]~reg0'
        Info: Total cell delay = 3.746 ns ( 44.74 % )
        Info: Total interconnect delay = 4.626 ns ( 55.26 % )
    Info: + Micro clock to output delay of source is 0.304 ns
    Info: + Longest register to pin delay is 6.804 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X16_Y14_N13; Fanout = 1; REG Node = 'led1[2]~reg0'
        Info: 2: + IC(3.698 ns) + CELL(3.106 ns) = 6.804 ns; Loc. = PIN_115; Fanout = 0; PIN Node = 'led1[2]'
        Info: Total cell delay = 3.106 ns ( 45.65 % )
        Info: Total interconnect delay = 3.698 ns ( 54.35 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 2 warnings
    Info: Peak virtual memory: 136 megabytes
    Info: Processing ended: Wed Apr 14 21:14:11 2010
    Info: Elapsed time: 00:00:01
    Info: Total CPU time (on all processors): 00:00:01