ka630.c

<B>Digital的Unix操作系统VAX 4.2源码</B>

extern	struct	uba_driver	sgdriver;
extern	struct	uba_driver	shdriver;
extern	struct	uba_driver	spdriver;
extern  struct  uba_driver      dshdriver;  /* DST/DSH32 Sync Device driver */

vaxstar_conf()
{
	register int i;
	extern int fl_ok;
	struct uba_device *ui;
	struct uba_ctlr *um;
	struct uba_hd *uhp;
	struct uba_driver *udp;
	extern int catcher[256];
	int (**ivec)();
	caddr_t addr;

	printf("KA410 processor ");
	if( fl_ok )
		printf("with an FPU\n");
	else
		printf("without an FPU\n");
	/*
	 * We now have the scb set up enough so we can handle
	 * interrupts some if they are waiting to happen.
	 */
	(void) spl0();

	uhp = &uba_hd[numuba];
	uhp->uh_vec = SCB_UNIBUS_PAGE(numuba);
	uhp->uh_lastiv = 0x200;
	for (i=0; i<(uhp->uh_lastiv/4); i++)
		uhp->uh_vec[i] = scbentry(&catcher[i*2], SCB_ISTACK);

	/*
	 * Say uba0 alive (so installation sizer will see it).
	 */
	config_set_alive("uba", 0, 0, -1);

	/*
	 * Check each unibus mass storage controller.
	 * For each one which is potentially on this uba,
	 * see if it is really there, and if it is record it and
	 * then go looking for slaves.
	 *
	 * For VAXstar, only config the system disk cntlr (sdc0)
	 * and SCSI TK50 tape cntlr (stc0).
	 */
	for (um = ubminit; udp = um->um_driver; um++) {
		if(um->um_alive)
			continue;
		if (udp == &sdcdriver)
			addr = (caddr_t)0x200c0000;
		else if (udp == &stcdriver)
			addr = (caddr_t)0x200c0080;
		else
			continue;
		cvec = 0x200;
		i = (*udp->ud_probe)(addr);
		if (i == 0)
			continue;
		um->um_ubanum = numuba;
		config_fillin(um);
		printf(" csr 0x%x ", addr);
		if (cvec == 0) {
			printf("zero vector\n");
			continue;
		}
		if (cvec == 0x200) {
			printf("didn't interrupt\n");
			continue;
		}
		printf("vec 0x%x, ipl 0x%x\n", cvec, br);
		um->um_alive = 1;
		um->um_hd = &uba_hd[numuba];
		um->um_addr = (caddr_t)addr;
		um->um_physaddr = (caddr_t)addr;
		udp->ud_minfo[um->um_ctlr] = um;
		for (ivec = um->um_intr; *ivec; ivec++) {
			um->um_hd->uh_vec[cvec/4] =
			    scbentry(*ivec, SCB_ISTACK);
			cvec += 4;
		}
		/*
		 * Only allows VAXstar disks/tapes (sd0->sd# and st0).
		 */
		for (ui = ubdinit; ui->ui_driver; ui++) {
			if ((ui->ui_driver != udp) || ui->ui_alive)
				continue;
			if ((*udp->ud_slave)(ui)) {
				ui->ui_alive = 1;
				ui->ui_ctlr = um->um_ctlr;
				ui->ui_ubanum = numuba;
				ui->ui_hd = &uba_hd[numuba];
				ui->ui_addr = (caddr_t)addr;
				ui->ui_physaddr = addr; /* rpb: swap on boot */
				if(ui->ui_dk && dkn < DK_NDRIVE)
					ui->ui_dk = dkn++;
				else
					ui->ui_dk = -1;
				ui->ui_mi = um;
				/* ui_type comes from driver */
				udp->ud_dinfo[ui->ui_unit] = ui;
				printf("%s%d at %s%d slave %d\n",
				    ui->ui_devname, ui->ui_unit,
				    udp->ud_mname, um->um_ctlr, ui->ui_slave);
				(*udp->ud_attach)(ui);
			}
		}
	}

	/*
	 * Configure remaining VAXstar devices, no others.
	 */
	for (ui=ubdinit; udp=ui->ui_driver; ui++) {
		if (udp == &ssdriver)
			addr = (caddr_t)0x200a0000;
		else if (udp == &smdriver)
			addr = (caddr_t)0x200f0000;
		else if (udp == &sgdriver)
			addr = (caddr_t)0x3c000000;
		else if (udp == &shdriver)
			addr = (caddr_t)0x38000000;
                else if (udp == &dshdriver)     /* DST32/DSH32 sync driver  */
                        addr = (caddr_t)0x38000000;
		else if (udp == &spdriver)	/* user device pseudo driver */
			addr = ui->ui_addr;	/* get CSR from config line */
		else
			continue;
		/*
		 * Following should never happen on a VAXstar.
		 */
		if ((ui->ui_ubanum != numuba && ui->ui_ubanum != '?') ||
		    ui->ui_alive || ui->ui_slave != -1)
			continue;
		cvec = 0x200;
		i = (*udp->ud_probe)(addr);
		if(i == 0)
			continue;
                if (udp == &dshdriver)      /* DST/DSH32 driver returns CSR */
                        addr = (caddr_t)i;  /* address from probe() routine */
		ui->ui_ubanum = numuba;
		config_fillin(ui);
		printf(" csr 0x%x ", addr);
		if (cvec == 0) {
			printf("zero vector\n");
			continue;
		}
		if (cvec == 0x200) {
			printf("didn't interrupt\n");
			continue;
		}
		printf("vec 0x%x, ipl 0x%x\n", cvec, br);
		ui->ui_hd = &uba_hd[numuba];
		for (ivec=ui->ui_intr; *ivec; ivec++) {
			ui->ui_hd->uh_vec[cvec/4] =
				scbentry(*ivec, SCB_ISTACK);
			cvec += 4;
		}
		ui->ui_alive = 1;
		ui->ui_addr = (caddr_t)addr;
		ui->ui_physaddr = 0;
		ui->ui_dk = -1;
		udp->ud_dinfo[ui->ui_unit] = ui;
		(*udp->ud_attach)(ui);
	}
	
	/* 
	 * Configure for ibus on CVAXstart
	 */
        config_set_alive("ibus", 0);
        for (ui=ubdinit; udp=ui->ui_driver; ui++) {
                if (udp == &lndriver && ui->ui_unit==0)
                        addr = (caddr_t) 0x200e0000;
                else
                        continue;
                /*
                 * Following should never happen on a CVAXstar.
                          */
                if (ui->ui_ubanum != -1 ||
                    ui->ui_alive || ui->ui_slave != -1)
                        continue;
                cvec = 0x200;
                i = (*udp->ud_probe)(addr);
                if(i == 0)
                        continue;
                ui->ui_adpt = 0;
                config_fillin(ui);
                printf(" csr 0x%x ", addr);
                if (cvec == 0) {
                        printf("zero vector\n");
                        continue;
                }
                if (cvec == 0x200) {
                        printf("didn't interrupt\n");
                        continue;
                }
                printf("vec 0x%x, ipl 0x%x\n", cvec, br);
                ui->ui_hd = &uba_hd[numuba];
                for (ivec=ui->ui_intr; *ivec; ivec++) {
                        ui->ui_hd->uh_vec[cvec/4] =
                                scbentry(*ivec, SCB_ISTACK);
                                      cvec += 4;
                }
                ui->ui_alive = 1;
                ui->ui_addr = (caddr_t)addr;
                ui->ui_physaddr = 0;
                ui->ui_dk = -1;
                udp->ud_dinfo[ui->ui_unit] = ui;
                (*udp->ud_attach)(ui);
        }

	/*
	 * Turn on parity error detection and clear any
	 * left over bits in the mser register (nxm from probe).
	 */
	((struct nb_regs *)nexus)->nb_mser =  QBM_LPE | QBM_PENB;
	/*
	 * Tell the console program that we've booted and
	 * that we would like to restart if the machine panics.
	 */
	((struct nb_regs *)nexus)->nb_cpmbx=RB_VS_RESTART;
	return(0);
}

short *ka630nexaddr(ioadpt,nexnum)
	int nexnum,ioadpt;
{

	return(NEXUVII);

}

char *ka630umaddr(ioadpt,nexnum)
	int ioadpt,nexnum;
{

	if (cpu_subtype == ST_MVAXII)
		return(QMEMUVII);
	else
		return(QMEMVAXSTAR);

}

u_short *ka630udevaddr(ioadpt,nexnum)
	int nexnum,ioadpt;
{

	return(QDEVADDRUVI);

}

ka630readtodr()
{

	u_int s,todr;
	struct tm tm;
	register struct qb_regs *qb_regs = (struct qb_regs *)nexus;

	/*
	 * If this is a VAXstar,
	 * call its readtodr() routine.
	 */
	if(cpu_subtype == ST_VAXSTAR)
		return(vaxstar_readtodr());

	/*
	 * Copy the toy register contents into tm so that we can
	 * work with. The toy must be completely read in 2.5 millisecs.
	 *
	 *
	 * Wait for update in progress to be done.
	 */
	while( qb_regs->qb_toycsra & QBT_UIP )
			;
	s = spl7();
	tm.tm_sec = qb_regs->qb_toysecs;
	tm.tm_min = qb_regs->qb_toymins;
	tm.tm_hour = qb_regs->qb_toyhours;
	tm.tm_mday = qb_regs->qb_toyday;
	tm.tm_mon = qb_regs->qb_toymonth;
	tm.tm_year = qb_regs->qb_toyyear;
	splx( s );

	todr = toyread_convert(tm);

	return(todr);
}

ka630writetodr(yrtime)
u_int yrtime;
{
	struct tm xtime;
	int s;
	register struct qb_regs *qb_regs = (struct qb_regs *)nexus;

	/*
	 * If this is a VAXstar,
	 * call its writetodr() routine.
	 */
	if(cpu_subtype == ST_VAXSTAR) {
		vaxstar_writetodr(yrtime);
		return;
	}

	toywrite_convert(&xtime,yrtime);

	qb_regs->qb_toycsrb = QBT_SETUP;
	s = spl7();
	qb_regs->qb_toysecs = xtime.tm_sec;
	qb_regs->qb_toymins = xtime.tm_min;
	qb_regs->qb_toyhours = xtime.tm_hour;
	qb_regs->qb_toyday = xtime.tm_mday;
	qb_regs->qb_toymonth = xtime.tm_mon;
	qb_regs->qb_toyyear = xtime.tm_year;
	/*
	* Start the clock again.
	*/
	qb_regs->qb_toycsra = QBT_SETA;
	qb_regs->qb_toycsrb = QBT_SETB;
	splx( s );

}

vaxstar_readtodr()
{

	u_int s,todr;
	struct tm tm;
	register struct nb_regs *nb_regs = (struct nb_regs *)nexus;

	/*
	 * All Vaxstar toy clock registers (including NVR)
	 * read/write bits 2 - 9 instead of 0 - 7.
	 */
	/*
	 * Copy the toy register contents into tm so that we can
	 * work with. The toy must be completely read in 2.5 millisecs.
	 *
	 *
	 * Wait for update in progress to be done.
	 */
	while( nb_regs->nb_toycsra & (QBT_UIP << 2) )
			;
	s = spl7();
	tm.tm_sec = ((nb_regs->nb_toysecs >> 2) & 0xff);
	tm.tm_min = ((nb_regs->nb_toymins >> 2) & 0xff);
	tm.tm_hour = ((nb_regs->nb_toyhours >> 2) & 0xff);
	tm.tm_mday = ((nb_regs->nb_toyday >> 2) & 0xff);
	tm.tm_mon = ((nb_regs->nb_toymonth >> 2) & 0xff);
	tm.tm_year = ((nb_regs->nb_toyyear >> 2) & 0xff);
	splx( s );

	todr = toyread_convert(tm);

	return(todr);
}

vaxstar_writetodr(yrtime)
u_int yrtime;
{
	struct tm xtime;
	int s;
	register struct nb_regs *nb_regs = (struct nb_regs *)nexus;

	toywrite_convert(&xtime,yrtime);

	nb_regs->nb_toycsrb = (QBT_SETUP << 2);
	s = spl7();
	nb_regs->nb_toysecs = (xtime.tm_sec << 2);
	nb_regs->nb_toymins = (xtime.tm_min << 2);
	nb_regs->nb_toyhours = (xtime.tm_hour << 2);
	nb_regs->nb_toyday = (xtime.tm_mday << 2);
	nb_regs->nb_toymonth = (xtime.tm_mon << 2);
	nb_regs->nb_toyyear = (xtime.tm_year << 2);
	/*
 	* Start the clock again.
 	*/
	nb_regs->nb_toycsra = (QBT_SETA << 2);
	nb_regs->nb_toycsrb = (QBT_SETB << 2);
	splx( s );

}

/*
 *  Function: ka630memerr()
 *
 *  Description: log memory errors in kernel buffer
 *
 *  Arguments: none
 *
 *  Return value: none
 *
 *  Side effects: none
 */
ka630memerr()
{
	int mser;
	struct el_rec *elrp;
	struct el_mem *mrp;

	if (cpu_subtype == ST_MVAXII)
		mser = ((struct qb_regs *)nexus)->qb_mser;
	else
		mser = ((struct nb_regs *)nexus)->nb_mser;
	if (mser & QBM_EMASK) {
	    elrp = ealloc(EL_MEMSIZE,EL_PRISEVERE);
	    if (elrp != NULL) {
		LSUBID(elrp,ELCT_MEM,EL_UNDEF,(cpu_subtype == ST_MVAXII)?ELMCNTR_630:ELMCNTR_VAXSTAR,EL_UNDEF,EL_UNDEF,EL_UNDEF);
		mrp = &elrp->el_body.elmem;
		mrp->elmem_cnt = 1;
		mrp->elmemerr.cntl = (mser & 0x300) >> 8;
		mrp->elmemerr.type = (mser & 0x80) ? ELMETYP_NXM : ELMETYP_PAR;
		mrp->elmemerr.numerr = 1;
		mrp->elmemerr.regs[0] = mser;
		if (cpu_subtype == ST_MVAXII) {
		    mrp->elmemerr.regs[1] = ((struct qb_regs *)nexus)->qb_caer;
		    mrp->elmemerr.regs[2] = ((struct qb_regs *)nexus)->qb_daer;
		} else {
		    mrp->elmemerr.regs[1] = ((struct nb_regs *)nexus)->nb_mear;
		    mrp->elmemerr.regs[2] = 0;
		}
		mrp->elmemerr.regs[3] = EL_UNDEF;
		EVALID(elrp);
	    }
	}
	return(0);
}