ka8800.c

<B>Digital的Unix操作系统VAX 4.2源码</B>

 * reporting occurs.  Thus we report at most once per memintvl.
 */

ka8800memenable ()
{
	register struct	nmi_reg *mcr;

	mcr = (struct nmi_reg *) mcrdata[0].mcraddr;
	mcr->memcsr3 |= NMI_C3_ENB_INT;

	return(0);

}


/*
 *  Function:
 *	ka8800memerr()
 *
 *  Description:
 *	log memory errors in kernel buffer by calling log_ka8800memerrs()
 *      and panic if told to do so.
 *
 *  Arguments:
 *	none
 *
 *  Return value:
 *	none
 *
 *  Side effects:
 *	none
 */

ka8800memerr()
{
        if (log_ka8800memerrs()==1)
	  panic("memerr");
	else
	  return(0);
}

log_ka8800memerrs()

/*-------------------------------------------------------*
 * function: Scan memory for errors and log any if found *
 *           Return recovery value back to the exception *
 *           handler that called the routine.            *
 *-------------------------------------------------------*/

{
	register struct	nmi_reg *mcr;
	register struct el_rec *elrp;
	register struct el_mem *mrp;
	register int junk, priority,type;

#ifdef lint
	junk = junk;
#endif lint


	mcr = (struct nmi_reg *) mcrdata[0].mcraddr;
	
	if ((mcr->memcsr2 & (NMI_C2_RDS|NMI_C2_BAD_DATA)) ||
	     (mcr->memcsr3 & NMI_C3_INTERNAL_ERR)) {
		priority = EL_PRISEVERE;
		type = 2;		

	} else if (mcr->memcsr2 & NMI_C2_CRD) {
		priority = EL_PRILOW;
		type = 1;
	} else {
		/* no memory errors --clear interrupt just in case */
		junk = mcr->memcsr4;
		return(0);
	}	
	elrp = ealloc(EL_MEMSIZE,priority);
	if (elrp != NULL) {
	    LSUBID(elrp,ELCT_MEM,cpu_systype,ELMCNTR_NMI,EL_UNDEF,EL_UNDEF,EL_UNDEF);
	    mrp = &elrp->el_body.elmem;
	    mrp->elmem_cnt = 1;
	    mrp->elmemerr.cntl = 1;
	    mrp->elmemerr.type = type;
	    mrp->elmemerr.numerr = 1;
	    mrp->elmemerr.regs[0] = mcr->memcsr0;
	    mrp->elmemerr.regs[1] = mcr->memcsr1;
	    mrp->elmemerr.regs[2] = mcr->memcsr2;
	    mrp->elmemerr.regs[3] = mcr->memcsr3;
	    EVALID(elrp);
	}
	/* clear error bits */
	mcr->memcsr2 = (mcr->memcsr2 & NMI_C2_ERR_BITS);

	/* disable crd's */
	mcr->memcsr3=(mcr->memcsr3& ~(NMI_C3_ENB_CRD))|NMI_C3_ENB_WRT;

	/* clear the NMI interrupt */
	junk = mcr->memcsr4;
	
	/* tell handler to crash burn and die if a non-recoverable error */

	if (priority == EL_PRISEVERE)
	  return(1);
	else
	  return(0);
}


/*
 * this routine sets the cache to the state passed.  enabled/disabled
 */

ka8800setcache(state)
int state;
{
	mtpr (CCR, state);
	return(0);
}

ka8800cachenbl()
{
	cache_state = 0x1;
	return(0);
}


ka8800tocons(c)
	register int c;
{
	register int timeo;

	timeo = 5000000;
	while ((mfpr (TXCS) & TXCS_RDY) == 0) {
		if (timeo-- <= 0) {
			return(0);
		}
	}
	mtpr (TXDB, c);
	return(0);
}

ka8800readtodr() {
	register u_int todr,data;
	register int s,i,j;

	s = spl7();
	while ((mfpr(TXCS) & TXCS_RDY) == 0);
	mtpr(TXDB,(N_TOY_READ|N_COMM));	
	i=0;
 	todr=0;
	while(i<4){
		j=0;
		while ((mfpr(RXCS) & RXCS_DONE) == 0) {
			j++;
			if (j==1000000) {
				splx( s );
				return(0);
			}
		}
 		data = mfpr(RXDB);
		if ((data&RXDB_ID) == N_TOY_DATA) {
			todr |= (data&RXDB_DATA)<< (8*i);
			i++;
		}
	}	
	splx( s );
	return(todr);
}
ka8800writetodr(yrtime) 
register u_int yrtime;
{
	register int s,i,j,todr;

	todr = TODRZERO + (100 * yrtime);

	s = spl7();
	while ((mfpr(TXCS) & TXCS_RDY) == 0);
	mtpr(TXDB,(N_TOY_WRITE|N_COMM));	
	i=0;
	while(i<4){
		j=0;
		while ((mfpr(TXCS) & TXCS_RDY) == 0) {
			j++;
			if (j==1000000) {
				splx( s );
				return;
			}
		}
 		mtpr(TXDB,(N_TOY_DATA + (todr&0xff)));
		todr = todr >> 8;
		i++;
	}	
	splx( s );
}


extern int txcs8800ie;
extern int rx8800ie;
extern struct tty cons[];
extern int tty8800rec[];

ka8800requeue(c) 
register int c;
{
	register struct tty *tp;
	register int i;

	switch (c&RXDB_ID) {
		case N_CSA1:
		case N_CSA2:
		case N_CONS_CNT:
		case N_CONS_MSG: 	
			{
		
			int rx8800_recieve();
			chrqueue(rx8800_recieve, c, 0);
			return;
			}
		case N_LCL_CONS: 
			i=0;
			break;

		case N_LCL_NOLOG: 
			i=1;
 			break;

		case N_RMT_CONS: 
			i=2;
			break;

		default:
			return;

	}
	tp = &cons[i];
	if (tp->t_state&TS_ISOPEN)
		chrqueue(linesw[tp->t_line].l_rint, c&0x7f, tp);
	if ((c&0x7f) == CSTOP)	tty8800rec[i] = 1;
	if ((c&0x7f) == CSTART) {
		tty8800rec[i] = 0;
		if (txcs8800ie == 0) {
			mtpr(TXCS,TXCS_IE);
			txcs8800ie = 1;
		}
	}

}



int rx8800error = 0;
int rx8800low = 0;
int rx8800code = 0;
extern struct rx5tab rx5tab;

rx8800_recieve(c) 
	int c;
{
	int id;

	if ((rx5tab.rx5_state & RX5BUSY) == 0) return;

	id = c & RXDB_ID;
	c = c & (~RXDB_ID); 

	switch (id) {


	case N_CONS_CNT:
		if (rx8800low) {
			rx8800code=c;
			rx8800low=0;
		}
		else {
			rx8800code |= (c<<8);
			cprintf("QIO error  %x \n",rx8800code);
			rx8800code = 0;
			break;
		}

	case N_CONS_MSG:

		switch (c&N_TYP_MASK) {

			case N_CSA1_STAT:
			case N_CSA2_STAT:
				c = c & ~(N_TYP_MASK);
				/* floppy completed ok? */
				if (c == N_CS_OK) {
					if ((rx5tab.rx5_buf->b_flags & B_READ)==0) {
						/* write is done start next trans action */
						if (rx5tab.rx5resid > 512)
							rx5tab.rx5resid -= 512;
						else rx5tab.rx5resid = 0;
					
						rx5tab.rx5blk++;

						if (rx5tab.rx5resid > 0)
							cs8800_start();
						else {
							iodone(rx5tab.rx5_buf);
							rx5tab.rx5_state &= ~RX5BUSY;
							wakeup((caddr_t)&rx5tab);
						}
					}
				} else {
					rx8800ie=0;
					rx8800low=1;
					rx5tab.rx5_buf->b_error = EIO;
					rx5tab.rx5_buf->b_flags |= B_ERROR;
					rx5tab.rx5_state &= ~ RX5BUSY;
					iodone(rx5tab.rx5_buf);
					wakeup((caddr_t) &rx5tab);
				}
				break;	
			
			default:
				printf("non-floppy status %x \n",c);
				break;
		}
		break;
	case N_CSA1:
	case N_CSA2:
		if (rx5tab.rx5_buf->b_flags & B_READ) {
			*rx5tab.rx5addr = (0xff &c);
	 		rx5tab.rx5addr++;
			rx5tab.count++;		

			if(rx5tab.count>=512) {
				/* write is done start next trans action */
				if (rx5tab.rx5resid > 512)
					rx5tab.rx5resid -= 512;
				else rx5tab.rx5resid = 0;
						
				rx5tab.rx5blk++;
	
				if (rx5tab.rx5resid > 0)
					cs8800_start();
				else {
					iodone(rx5tab.rx5_buf);
					rx5tab.rx5_state &= ~RX5BUSY;
					wakeup((caddr_t)&rx5tab);
				}
			}
		}
		break;
	}

}

cs8800_start() {
	register int s;

	rx5tab.cmdcount = 3;
	rx5tab.count = 0;
	rx5tab.command[1] =  (rx5tab.command[1] & 0xff00) |
				(rx5tab.rx5blk & 0xff);
	rx5tab.command[0] =  (rx5tab.command[0] & 0xff00) |
				((rx5tab.rx5blk >> 8) & 0xff);
	s=spl5();
	rx8800ie=1;
	if (txcs8800ie == 0) {
		txcs8800ie=1;
		mtpr(TXCS,TXCS_IE);
	}
	splx(s);
}
rx8800_trans() 
{
	int s;
	s=spl5();

	if ((rx5tab.rx5_state & RX5BUSY) == 0) rx8800ie=0;
	else {

		if (rx5tab.cmdcount > 0) {
			while((mfpr(TXCS)&TXCS_RDY) == 0) ;
			rx5tab.cmdcount--;
			mtpr(TXDB,rx5tab.command[rx5tab.cmdcount]);
			rx8800ie=1;
		} else {
			if (rx5tab.rx5_buf->b_flags & B_READ) {
				/* command is transmited */
				rx8800ie=0;
				
			} else {

				mtpr(TXDB, ((*rx5tab.rx5addr & 0xff)|rx5tab.id));
				
 				rx5tab.rx5addr++;
				rx5tab.count++;		
				rx8800ie=1;
				/* done writing to buffer */
				if (rx5tab.count==512) {
					 rx8800ie=0;
				}
			}

		}
	}
	if (txcs8800ie == 0) {
		txcs8800ie=1;
		mtpr(TXCS,TXCS_IE);
	}
	splx(s);
}

ka8800startrx() {

register u_short dn;
register int s;

	rx5tab.cmdcount =3;
	rx5tab.count =0;
	dn = (minor(rx5tab.rx5_buf->b_dev)>>3) & 07;


	if (rx5tab.rx5_buf->b_flags & B_READ ) { 
		rx5tab.command[2] = N_CSA_CMD | ((dn-1) << 4) | N_CS_READ;
	}
	else {
		rx5tab.command[2] = N_CSA_CMD | ((dn-1) << 4) | N_CS_WRITE;
	}

	rx5tab.id = N_CSA1 << ((dn-1)*2);
	rx5tab.command[1] = N_CSA_CMD | (rx5tab.rx5blk & 0xff);
	rx5tab.command[0] =  N_CSA_CMD | ((rx5tab.rx5blk >> 8)&0xff);

	s=spl5();
	rx8800ie=1;

	if (txcs8800ie == 0) {
		mtpr(TXCS,TXCS_IE);
		txcs8800ie = 1;
	}

	splx(s);
}