ka6400.c

<B>Digital的Unix操作系统VAX 4.2源码</B>

 * XRP only!
 *
 * The following register exists on both XRP and XMP, but the definitions
 * here only exist on XRP.
 *
 * Bits within the Rigel VAX6000-4xx c-chip status register, BCSTS
 * (as defined in the XRP CPU spec rev 1.0)
 *	the following bits may be read or written by the user.  writing a '1' 
 *	to this bit will clear the bit.  writing a '0' to this bit has no 
 *	effect on the bit.  the hardware may read or write this bit (WC):
 *		BCSTS_STATUS_LOCK
 *	the following bits may be read by the user but not written.  only 
 *	hardware can change the value of the bit.  user writes to this bit 
 *	are ignored (RO):
 *		BCSTS_BTS_PERR
 *		BCSTS_P1TS_PERR
 *		BCSTS_P2TS_PERR
 *		BCSTS_BUS_ERR
 *		BCSTS_BTS_COMPARE
 *		BCSTS_BTS_HIT
 *		BCSTS_P1TS_HIT
 *		BCSTS_P2TS_HIT
 *		BCSTS_DAL_CMD
 *		BCSTS_IBUS_CYCLE
 *		BCSTS_PRED_PARITY
 */

#define	BCSTS_STATUS_LOCK	0x00000001	/* WC */
#define	BCSTS_BTS_PERR		0x00000002	/* RO */
#define	BCSTS_P1TS_PERR		0x00000004	/* RO */
#define	BCSTS_P2TS_PERR		0x00000008	/* RO */
#define	BCSTS_BUS_ERR		0x00000010	/* RO */
#define	BCSTS_BTS_COMPARE	0x00020000	/* RO */
#define	BCSTS_BTS_HIT		0x00040000	/* RO */
#define	BCSTS_P1TS_HIT		0x00080000	/* RO */
#define	BCSTS_P2TS_HIT		0x00100000	/* RO */
#define	BCSTS_DAL_CMD		0x01e00000	/* RO - 4 bits */
#define	BCSTS_IBUS_CYCLE	0x02000000	/* RO */
#define	BCSTS_PRED_PARITY	0x04000000	/* RO */

/*
 * XMP only!
 *
 * The following register exists on the XMP and XRP modules, but the
 * definitions here are unique to the XMP.
 *
 * Bits within the Mariah VAX6000-5xx c-chip status register, BCSTS
 * (as defined in the XMP CPU spec rev 1.0)
 *	the following bits may be read or written by the user.  writing a '1' 
 *	to this bit will clear the bit.  writing a '0' to this bit has no 
 *	effect on the bit.  the hardware may read or write this bit (WC):
 *		BCSTS_BTS_TPERR
 *              BCSTS_BTS_VDPERR
 *              BCSTS_I_PERR
 *              BCSTS_FILL_ABORT
 *              BCSTS_AC_PERR
 *	the following bits may be read by the user but not written.  only 
 *	hardware can change the value of the bit.  user writes to this bit 
 *	are ignored (RO):
 *              BCSTS_ERR_SUMMARY
 *              BCSTS_SECOND_ERR
 *		BCSTS_BTS_HIT_XMP
 *		BCSTS_BTS_COMPARE_XMP
 *		BCSTS_PPG
 *		BCSTS_BTS_PARITY
 *		BCSTS_IBUS_CYCLE_XMP
 *		BCSTS_IBUS_CMD
 *		BCSTS_DAL_CMD_XMP
 *		BCSTS_DMG_L
 *		BCSTS_SYNC_L
 *              BCSTS_AC_PARITY
 *              BCSTS_OREAD_PENDING
 */

#define	BCSTS_ERR_SUMMARY	0x00000001	/* RO */
#define	BCSTS_BTS_TPERR		0x00000002	/* WC */
#define	BCSTS_BTS_VDPERR	0x00000004	/* WC */
#define	BCSTS_I_PERR		0x00000030	/* WC */
#define BCSTS_FILL_ABORT        0x00000040      /* WC */
#define BCSTS_AC_PERR           0x00000080      /* WC */
#define BCSTS_SECOND_ERR        0x00000100      /* RO */
#define	BCSTS_BTS_HIT_XMP	0x00008000	/* RO */
#define	BCSTS_BTS_COMPARE_XMP	0x00010000	/* RO */
#define	BCSTS_PPG		0x00020000	/* RO */
#define	BCSTS_BTS_PARITY	0x000C0000	/* RO */
#define	BCSTS_IBUS_CYCLE_XMP	0x00100000	/* RO */
#define	BCSTS_IBUS_CMD  	0x00200000	/* RO */
#define	BCSTS_DAL_CMD_XMP       0x03C00000	/* RO - four bits */
#define BCSTS_DMG_L             0x04000000      /* RO */
#define BCSTS_SYNC_L            0x08000000      /* RO */
#define BCSTS_AC_PARITY         0x10000000      /* RO */
#define BCSTS_OREAD_PENDING     0x20000000      /* RO */

/*
 * KA6400 machine check exception handler.
 *      Categories of errors causing machine checks:
 *	. Floating point processor problems.
 *	. Memory management, interrrupt, microcode/CPU errors
 *	. Primary cache read error - tag parity errors, data parity errors
 *	. DAL error on memory read - DAL data parity errors, B-cache RAMs, 
 *	  REXMI-->REX520 parity errors
 *	  ERR_L terminator, XBER notified errors, RSSC DAL timeouts
 *	. DAL error on memory write or flush write buffers, ERR_L terminator,
 *	  RSSC DAL timeouts
 *	. Vector unit errors
 *
 * This handler is also executed for ka6500 machine checks.  The routine will
 * use cpu_sub_subtype in places where cpu-specific code must be executed.
 *
 * Environment:
 *	IPL		0x1f
 *	stack		Interrupt stack
 *	SCB vector <1:0> = 01.
 *
 * Parameter:
 * mcf 	Points to machine check frame.  For Ka6400, the
 *	frame format:
 *
 *	. byte count	(0x18)
 *	. R bit (VAX restart bit) in <31>, mcheck code in <0:15>
 *	  Valid machine check codes are:
 *	  1, 2, 3, 4, 5, 8, 9, 0xa, 0xb, 0xc, 0xd, 0x10, 0x11, 0x12,
 *	  0x13, and 0x14.
 *	. Virtual Address processed by REX520 M-box, (not
 *	  necessarily relevant.
 *	. VIBA - The REX520 M-box prefetch virtual instruction
 *	  buffer address at the time of the fault.
 *	. ICCS.SISR   Interrupt state information in the following format:
 *		Bits	Contents
 *		<22>	ICCS<6>
 *		<15:1>	SISR<15:1>
 *	. Internal State, of the following format:
 *	  - bits<3:0>  RN, the value of the E-box RN register at the
 *	    time of the fault, possibly indicating the last GPR referenced
 *	    by the E-box during specifier or instruction flows.
 *	  - bits<7:4> Undefined
 *	  - bits<15:8> Opcode, the opcode (2nd if two-byte) of the instr
 *	    being processed at the time of the fault.
 *	  - bits<17:16> DL, the current setting of the E-box data length
 *	    latch, may relate to the last (or forthcoming) memory reference.
 *	    value: 0     byte
 *		   1     word
 *		   2     long, f_floating
 *		   3     quad, d_floating, g_floating
 *	  - bits<20:18> AT, the current setting of the E-box address type
 *	    latch, possibly relating to the last (or upcoming) memory
 *	    reference.
 *	    value: 0     read
 *		   1     write
 *		   2     modify
 *		   3     unassigned, REX520 chip error
 *		   4     unassigned, REX520 chip error
 *		   5     address
 *		   6     variable bit
 *		   7     branch
 *	  - bits<23:21> Undefined
 *	  - bits<31:24> Delta PC, difference in the values of the current
 *	    incremented PC at the time of the machine check was detected
 *	    and the PC of the instruction opcode.  This field shouldn't
 *	    be used by software to make recovery decisions as it is internal
 *	    pipeline specific.
 *	. SC, Internal microcode-accessible register.
 *	. Program counter.
 *	. PSL.
 *
 * Returns:
 *	0
 */
ka6400machcheck (mcf)
register struct el_mc6400frame *mcf;
{
	register int cpunum;
	register struct xrp_reg *xrp_node;
	register int xminode;
	int	restartable;		/* Flag set if we can restart instr*/
	int	must_panic;		/* Flag set if we must panic	*/
	struct xmidata *xmidata;
	register struct el_mc6400frame *framep;
	register struct el_mc6500frame *xmp_framep;
	register struct el_rec *elrp;
	struct el_mck *elmckp;
	register int mcode;
	long	time_now;

	int	r_bit;			/* Value of R bit in mcheck frame */
	int	fpd;			/* Value of PSL<fpd> in mcheck frame*/
	int	uwp;			/* Value of RCSR<uwp> 		  */
	int     trap2;                  /* Value of  */
	long	vector_mchk_type;
	int	ls_bug;			/* true if a hardware bug is found */
					/* this should never happen since  */
					/* we have installed the fix in    */
					/* our lab and the field should    */
					/* never get a board with the bug, */
					/* but ....                        */

	time_now = mfpr(TODR);		/* Log the current time	*/

	restartable = must_panic  = 0;	/* Initial assumption	*/

	cpunum=CURRENT_CPUDATA->cpu_num;


	if (mchk_data[cpunum].mchk_in_progress == 0) {
		/* if no machine check in progress, we're ok */
		mchk_data[cpunum].mchk_in_progress++;
		}
	else	{
		/* nested machine check, we're in big trouble	*/
		asm("halt");
	}

	mtpr(MCESR,0);	/* Tell hardware we acknowledge the machine check */
	snapshot_registers(cpunum); /* Take a snapshot of registers */

	/*
	 * The following bits are always checked to determine
	 * if the instruction can be restarted.  Lets read them in
	 * now.
	 */
	r_bit = (mcf->mcode & 0x80000000) >> 31;
	fpd = (mcf->psl & 0x08000000) >> 27;

	if(cpu_sub_subtype != MARIAH_VARIANT) {
		uwp = (error_data[cpunum].s_rcsr & 0x100000) >> 20;
		ka6400_disable_cache();/* to minimise chance of nested errors */
	}
	else {
		uwp =   (error_data[cpunum].s_xbeer0 & 0x800) >> 11; /* XMP */
		trap2 = (error_data[cpunum].s_pcsts & 0x40) >> 6;    /* XMP */
	        error_disable_cache();
	}
	xmidata = get_xmi(0);
	xrp_node = (struct xrp_reg *)xmidata->xmivirt + (rssc->s_iport & 0xf); 

	/*
	 * Case of the type of machine check, we may be able
	 * to recover from the machine check under certain conditions.
	 */
	mcode = mcf->mcode & 0xffff;
	switch (mcode) {
	case 1:	/* Protocol error during F-chip operand/result transfer */
	case 2:	/* Illegal opcode detected by F-chip */
	case 3:	/* Operand parity error detected by F-chip */
	case 4:	/* Unknown status returned by F-chip */
	case 5:	/* Returned F-chip result parity error */
		/* 
		 * The above errors are restartable under the following
		 * conditions:
		 * 	1) VAX restart bit set (R==1), and
		 *	2) FPD==0 (FPD of the saved PSL on mcheck frame), and
		 *	3) UWP==0 (REXMI RCSR unlock-write-pending clear).
		 * If the error re-occurs, disable the F-chip by writing
		 * a zero to ACCS<1>
		 */
		if (r_bit&& (fpd==0) && (uwp==0)) {
			/* Machine check is restartable */
			restartable = 1;
			if (mcode == (mchk_data[cpunum].mcode & 0xffff)) {
				/* Error occurred previously, turn off FPA */
				mtpr(ACCS,mfpr(ACCS) & ~2);
			}
		}
		break;
		
	case 8: /* TB miss status generated in ACCVIO/TNV microflow */
	case 9:	/* TB hit status generated in ACCVIO/TNV microflow */
	case 0xa: /* Undefined INT.ID value during interrupt service */
		/*
		 * The above are restartable when:
		 *  ((R==1)||(FPD==1)) && (UWP==0)
		 */
		if ((fpd | r_bit) && (uwp==0)) {
			/* Machine check is restartable */
			restartable = 1;
		}
		break;

	case 0xb: /* Undefined state bit combination in MOVCx */
		/* 
		 * Problem due to a MOVCx instruction, if software
		 * determines that no specifier have been over-written
		 * (MOVCx destroys R0-R5 and memory due to string writes),
		 * the instruction can be restarted from the beginning
		 * by clearing PSL<FPD>.  This should be done only if
 		 * the source and destination strings don't overlap and
		 *   (FPD==1) &&(UWP==0).
		 *
		 * Note: We can't determine if string overlaps, so we don't
		 * restart the instruction, just to be safe.
		 */
		break;

	case 0xc: /* Undefined trap code produced by I-box */
		/*
		 * Restartable when:
		 *   (R==1) && (FPD==0) && (UWP==0)
		 */
		if (r_bit && (fpd==0) && (uwp==0)) {
			restartable = 1;
		}
		break;

	case 0xd: /* Undefined control store address reached */
		/*
		 * Restartable when
		 *   ((R==1) || (FPD==1)) && (UWP==0)
		 */
		if ((r_bit | fpd) && (uwp==0)) {
			restartable = 1;
		}
		break;

	case 0x10: 
		/*
		 * P-cache tag or data parity error during read.
		 * PCSTS<TAG_PARITY_ERROR> or PCSTS<P_DATA_PARITY_ERROR>
		 * bits should be set, if neither bits is set,
		 * the state is inconsistent, panic.
		 * If either bit is set, do a full memory error recover.
		 * We can restart the instruction
		 * if ((R==1) || (FPD==1)) && (UWP==0) && (TRAP2==0)
		 */
		if ((error_data[cpunum].s_pcsts & 0x500)==0) {
			/* neither error bit set, panic */
			must_panic = 1;
		}
		else {	
			recover_mem_error();
		        if(cpu_sub_subtype == MARIAH_VARIANT) {
			  if(time_now - pcache_errtime[cpunum] < 500) {
			    pcache_error[cpunum]++;
			  }
			  else {
			    pcache_errtime[cpunum] = time_now;
			  }
			}
			if ((r_bit | fpd) && (uwp==0) && 
			    ((error_data[cpunum].s_pcsts & PCSTS_TRAP2)==0)) {
				restartable = 1;
			}
		}
		break;

	case 0x11: /* DAL bus or data parity error during read */
		/*
		 * Either PCSTS<DAL_DATA_PARITY_ERROR> or 
		 * PCSTS<BUS_ERROR> should be set.  If neither bit
		 * is set, or if both bits are set, something is
		 * seriously wrong, panic.
		 *
		 * If PCSTS<BUS_ERROR> is set, we have a bus error on
		 * D-stream read, which may be a RSSC bus timeout on
		 * D-stream read, or a memory error on requested quadword
		 * of D-stream read.  In either case, we don't really
		 * know how to recover, so panic.
		 *
		 * Thus if and only if PCSTS<DAL_DATA_PARITY_ERROR> is
		 * set can we attempt a restart.  A restart can be performed
		 * if  ((R==1) || (FPD==1)) && (UWP==0) && (TRAP2==0)
		 */
		if ((error_data[cpunum].s_pcsts & 0xa00)==0x200) {
			recover_mem_error();
		        if(((error_data[cpunum].s_pcsts & 0x1080) == 0x1080) && 
                           (cpu_sub_subtype == MARIAH_VARIANT)) {
			  if(time_now - bcache_errtime[cpunum] < 500) {
			    bcache_error[cpunum]++;
			  }
			  else {
			    bcache_errtime[cpunum] = time_now;
			  }
			}
			if ((r_bit | fpd) && (uwp==0) && 
			    ((error_data[cpunum].s_pcsts & PCSTS_TRAP2)==0)) {
				restartable = 1;
			}
		}
		else	{
			/* inconsistent PCSTS, or <BUS_ERROR> */
			must_panic = 1;
		}
		break;

	case 0x12: /* DAL bus error on write or clear write buf */
		if(cpu_sub_subtype == MARIAH_VARIANT)
		   /*
		    * MSSC Bus Timeout on Write or Clear-write-buffer.
		    *
		    * PCSTS<BUS_ERROR, TRAP1> both set, and
		    * SSCBTR<RWT,BTO> bot set
		    */
		   if(((error_data[cpunum].s_pcsts & 0x880) == 0x880) &&
		      ((error_data[cpunum].s_sscbtr & 0xc0000000) == 0xc0000000)) {
		        recover_mem_error();
		   }
		   /*
		    * Backup Cache Error on Write.
		    *
		    * PCSTS<BUS_ERROR, TRAP1 both set, 
		    * BCSTS: DMG_L, SYNC_L, and ES set, DAL_CMD = write,
		    *        and either TPERR or VDPERR set.
		    */
		   else if(((error_data[cpunum].s_pcsts & 0x880) == 0x880) &&
			   ((error_data[cpunum].s_bcsts & 0x0fc00001) == 0x0dc00001) &&
			   ((error_data[cpunum].s_bcsts & 0x6) != 0x0)) {
		             recover_mem_error();
		   }
		   /*
		    * Memory Error on Write.
		    *
		    * XBE: TTO|CNAK|WDNAK set,
		    * XFAER: XMI_CMD = write,
		    * PCSTS<TRAP1, BUS_ERROR> both set.
		    */
		   else if(((error_data[cpunum].s_xber & 0x10a000) != 0) &&
			   ((error_data[cpunum].s_xfaer0 & 0xc0000000) == 0x40000000) &&
			   ((error_data[cpunum].s_pcsts & 0x880) == 0x880)) {
			   /* Memory Error on Write */
		               xrp_node->xrp_xbe = error_data[cpunum].s_xber;
		   }
		must_panic=1;
		break;
	case 0x13: /* Undefined bus error microtrap */
		must_panic=1;
		break;