ka6400.c

<B>Digital的Unix操作系统VAX 4.2源码</B>

#ifndef lint
static char *sccsid = "@(#)ka6400.c	4.10	ULTRIX	4/11/91";
#endif lint

/************************************************************************
 *									*
 *			Copyright (c) 1990 by				*
 *		Digital Equipment Corporation, Maynard, MA		*
 *			All rights reserved.				*
 *									*
 *   This software is furnished under a license and may be used and	*
 *   copied  only  in accordance with the terms of such license and	*
 *   with the  inclusion  of  the  above  copyright  notice.   This	*
 *   software  or  any  other copies thereof may not be provided or	*
 *   otherwise made available to any other person.  No title to and	*
 *   ownership of the software is hereby transferred.			*
 *									*
 *   The information in this software is subject to change  without	*
 *   notice  and should not be construed as a commitment by Digital	*
 *   Equipment Corporation.						*
 *									*
 *   Digital assumes no responsibility for the use  or  reliability	*
 *   of its software on equipment which is not supplied by Digital.	*
 *									*
 ************************************************************************/

/***********************************************************************
 *
 * Modification History:
 *
 * 11-Apr-91	dlh
 *	ka6400conf()
 *		- get vpmask from cca_vec_enabled field
 *		- correct printf when xrv is enabled
 *		- write 0 to VP enabled bit in ACCS when boot CPU is not in 
 *		  vpmask.
 *		  note: question write of 0 to ACCS when CPU is not in vpmask.
 *		        this may not be necessary.
 *	
 *	ka6400machcheck()
 *		removed debug prinf's
 *	
 *	ka6400harderr()
 *		comment out debug printf's
 *	
 *	ka6400softerr()
 *		removed debug printf's
 *
 * 09-Apr-91	szczypek
 *		Added call to recover_mem_error() in ka6500softerr().
 *		Call made if CRD detected.  Need to call this routine
 *		in order to clear out CRD error bit in XBER.
 *
 * 21-Dec-90	szczypek
 *		Added code to clear_xrperr() routine which will clear
 *		out all pcache, bcache, and scc error bits as well as
 *		xbe (and xbeer on Mariah).  This code is required in
 *		order to ensure that the primary cache is on.
 *		
 * 20-dec-90	dlh
 *		added parameter to vp_reset() call
 *
 * 03-Dec-90	szczypek
 *		Ensured that ka6400harderr() and ka6400softerr() passed
 *		back return values for ka6500harderr() and
 *		ka6500soferr().  Added return value to ka6400setcache()
 *		and ka6500harderr() to satify LINT.  Added line to
 *		initialize xmidata pointer in ka6400machcheck().
 *
 * 06-Nov-90	szczypek
 *		add error handling (retry) code for rer/rse/tto errors
 *		on idents.  For VAX6000-5x0.
 *
 * 10-oct-90	dlh
 *		add vector support for the Mariah (VAX6000-5xx)
 *
 * 4-sep-90	dlh
 *		add vector support to:  ka6400machcheck(), ka6400conf(),
 *		 ka6400harderr()
 *
 * 02-may-90    szczypek
 *		add support for XMP cpu.  Will reuse as much XRP code as
 *              possible, with IF-THEN-ELSE being used in areas where cpu
 * 		specific code must be executed.
 *
 * 12-jan-90	haeck
 *		add a check for CRD (Corrected Read) memory error packets;
 *		prevent creation of an error packet if it is a CRD error.
 *
 * 08-dec-89 	jaw remove prinf in init routine.
 *
 * 29-Nov-89    Paul Grist
 *      modified ka6400machcheck() to call log_xmi_bierrors and log_xmierrors
 *      to look for any pending XBI or VAXBI errors.
 *
 * 24-May-89	darrell
 *	Changed the #include for cpuconf.h to find it in it's new home --
 *	sys/machine/common/cpuconf.h
 *
 * 24-May-89	darrell
 *	Removed the v_ prefix from all cpusw fields, removed cpup from any
 *	arguments being passed in function args.  cpup is now defined
 *	globally -- as part of the new cpusw.
 *
 * 05-Mar-89	Tom Kong
 *		Added workaround so that the cache manipulation code
 *		works for both 1st pass and 2nd pass XRPs.  Removed
 *		conditional compilation based on revision level of
 *		the XRP.  Improved soft error handling for Rigel.
 *
 * 1-Feb-89	Tom Kong
 *		Added work-around for 2nd pass XRP bugs.
 *		My understanding of the bug:  If an XMI bus timeout occurs
 *		at some critical point in the XMI state machine, the
 *		2nd Error bit in the RCSR will be set on the first occurence
 *		of this error (the bit shouldn't be set).  Since this bit
 *		drives the hard error interrupt line, an extraneous hard
 *		error interrupt is posted.
 *		Solution: the machine check handler, the hard error handler,
 *		and the soft error handler all clear the error bits in the
 *		RCSR and XBE that were associated with the errors being
 *		serviced.  The hard error handler can treat the error as
 *		extraneous under the following three conditions:
 *		1) If RCSR<4> (2nd error bit) is set, and no other error
 *		   bits in the XBE and RCSR are set other than XBE<27>,
 *		   XBE<23>, XBE<19>, and XBE<14>.  This condition indicates
 *		   the 2nd error bit was erroneously set during a machine
 *		   check.
 *		2) RCSR<4> and RCSR<27> are set and no other error bits in
 *		   the XBE or RCSR are set other than XBE<27>, XBE<23>,
 *		   XBE<19>, XBE<18>, XBE<17>, XBE<16>, XBE<14>, and XBE<13>.
 *		   This condition indicates the 2nd error bit was erroneously
 *		   set due to a cache-fill error.
 *		3) RCSR and XBER have no error bit set.
 *
 * 10-Jan-89	Kong
 *		Modified to run with SMP kernel.
 *
 * 6-Sep-88	Tom Kong
 *		Created this file from ka6200.c
 *
 **********************************************************************/

#include "../machine/pte.h"
#include "../h/param.h"
#include "../h/conf.h"
#include "../h/time.h"
#include "../h/errno.h"
#include "../h/systm.h"
#include "../h/types.h"
#include "../h/map.h"
#include "../h/buf.h"
#include "../h/errlog.h"
#include "../h/ioctl.h"
#include "../h/tty.h"
#include "../h/cpudata.h"
#include "../../machine/common/cpuconf.h"
#include "../h/kmalloc.h"
#include "../h/vmmac.h"

#include "../machine/cons.h"
#include "../machine/cons.h"
#include "../machine/cpu.h"
#include "../machine/clock.h"
#include "../machine/mtpr.h"
#include "../machine/mem.h"
#include "../machine/nexus.h"
#include "../machine/scb.h"
#include "../io/uba/ubareg.h"
#include "../io/uba/ubavar.h"
#include "../io/bi/buareg.h"
#include "../machine/sas/vmb.h"
#include "../machine/ka6400.h"
#include "../machine/cvax.h"

#include "../io/xmi/xmireg.h"
#include "../io/xmi/xmareg.h"

#include "../h/proc.h"
#include "../machine/vectors.h"

/*#define KILL_USER*/
#ifdef KILL_USER		/* Only do it when not running ASMP */
/*
 * Need u symbols, ...etc to terminate user process
 */
#include "../h/user.h"	
#include "../h/proc.h"
#include "../machine/psl.h"
#endif

#ifndef	KILL_USER	/* need u symbols for vp stuff */
#include "../h/user.h"
#endif

extern struct bidata bidata[];
extern int cache_state;
extern int nNVAXBI;
extern char *calypso_ip_addr;		/* In spt.s	*/
extern int fl_ok;			/* In locore.s  */

char *mcrvax[] = {
	"Unknown machine check type code 0",			    /* 0 */
	"Protocol error during F-chip operand/result transfer",     /* 1 */
	"Illegal opcode detected by F-chip",			    /* 2 */
	"Operand parity error detected by F-chip",		    /* 3 */
	"Unknown status returned by F-chip",			    /* 4 */
	"Returned F-chip result parity error",			    /* 5 */
	"Unknown machine check type code 6",			    /* 6 */
	"Unknown machine check type code 7",			    /* 7 */
	"TB miss status generated in ACCVIO/TNV microflow",	    /* 8 */
	"TB hit status generated in ACCVIO/TNV microflow",	    /* 9 */
	"Undefined INT.ID value during interrupt service",	    /* a */
	"Undefined state bit combination in MOVCx",		    /* b */
	"Undefined trap code produced by I-box",		    /* c */
	"Undefined control store address reached",		    /* d */
	"Unknown machine check type code 0xe",			    /* e */
	"Unknown machine check type code 0xf",			    /* f */
	"P-cache tag or data parity error during read",		    /* 10*/
	"DAL bus or data parity error during read",		    /* 11*/
	"DAL bus error on write or clear write buff",		    /* 12*/
	"Undefined bus error microtrap",			    /* 13*/
	"Vector unit error",					    /* 14*/
        "Error on I-stream read",                                   /* 15*/  /* Added for XMP support */
	"Unknown machine check type code > 0x15"  		    /* others */ /* Modified for XMP support */
};


/*
 * Array of virtual addresses that when written,
 * cause an IP interrupt to be sent.
 *
 * Usage:
 *	*calypso_ip[n] = 0	to send an IP interrupt to node n
 */
char *calypso_ip[16];		

/*
 * Data structure to keep track of the latest machine check information,
 * One structure per processor.
 */
struct	mchk_data {
long	mchk_in_progress;	/* Flag set while we're running mcheck code */
long	time;			/* time stamp of the error */

/* The following are a copy of the machine check frame */
long	mcode;			/* R bit and machine check code	   */
long	vaddr;			/* virtual address		   */
long	viba;			/* */
long	iccs_sisr;		/* ICCS and SISR		   */
long	istate;			/* Internal state		   */
long	sc;			/* SC */
long	pc;			/* program counter		   */
long	psl;			/* PSL				   */
};
struct	mchk_data *mchk_data;	/* Pointer to an array		   */

/*
 * XMP-specific registers which differ from XRP.
 */

#define XMP_BCIDX	112
#define XMP_BCSTS	113
#define XMP_BCCTL	114
#define XMP_BCERA       115
#define XMP_BCBTS	116
#define XMP_BCDET       117
#define XMP_BCERT       118

#define XMI_WCDE0       0x80000
#define XMI_WCDE1       0x8000000

#define XBEER0_ACPE     0x20000000
#define XBEER0_WDPE     0x40000000

#define EVEN_PARITY     0
#define ODD_PARITY      1

extern int cpu_sub_subtype;

int pcache_disable[MAXCPU];
int bcache_disable[MAXCPU];
unsigned int pcache_errtime[MAXCPU];
unsigned int bcache_errtime[MAXCPU];
int pc_enable[MAXCPU];
int bc_enable[MAXCPU];
unsigned int bcache_error[MAXCPU];
unsigned int pcache_error[MAXCPU];

/*
 * Data structure to store snapshot of hardware registers.
 * One structure per XRP processor.
 */

struct error_data {
/* The following are a snapshot of various hardware registers */
long	s_rcsr;			/* REXMI Control & Status Register (XRP only)*/
long	s_xber;			/* REXMI/MAXMI Bus Error Register	*/
long	s_xfadr;		/* REXMI/MAXMI Failing Address Register	*/
long	s_sscbtr;		/* RSSC/MSSC Bus Timeout Register	*/
long	s_bcctl;		/* C-chip Control Register		*/
long	s_bcsts;		/* C-chip Status Register		*/
long	s_bcerr;		/* C-chip Error Address Register	*/
long	s_pcsts;		/* P-cache Status Register		*/
long	s_pcerr;		/* P-cache Error Address Register	*/
long	s_vintsr;		/* C-chip Vector Interface Error Status */
/* Below are the XMP-specific registers */
long    s_xfaer0;               /* MAXMI Failing Address Extension Reg0 */
long    s_xbeer0;               /* MAXMI Bus Error Extension Register 0 */
long    s_wfadr0;               /* MAXMI Failing Address Reg for Wback0 */
long    s_wfadr1;               /* MAXMI Failing Address Reg for Wback1 */
long    s_fdal0;                /* MAXMI Failing DAL register 0         */
long    s_fdal1;                /* MAXMI Failing DAL register 1         */
long    s_fdal2;                /* MAXMI Failing DAL register 2         */
long    s_fdal3;                /* MAXMI Failing DAL register 3         */
long    s_bcert;                /* C-chip Error Tag Register            */
};
struct	error_data *error_data;	              /* Pointer to an array     */

/* the following defines should be in mtpr.h, but since we don't want the 
 * world to rebuild for a FT patch ....
 */
/*
 * Bits within the Rigel VAX6000-4xx P-cache status register
 * (as defined in the XRP CPU spec rev 1.0).  All but one are the same for
 * XMP also.
 *	the following bits may be read or written by the user or the
 *	hardware: PCSTS_FORCE_HIT
 *		  PCSTS_ENABLE_PTS 
 *		  PCSTS_ENABEL_REFRESH  (XRP only)
 *	the following bits may only be written by the user.  if this bit is
 *	read it will always read as a 0:
 *		  PCSTS_FLUSH_CASHE
 *	the following bits may be read or written by the user.  writing a '1' 
 *	to this bit will clear the bit.  writing a '0' to this bit has no 
 *	effect on the bit.  the hardware may read or write this bit:
 *		  PCSTS_INTERRUPT
 *		  PCSTS_TRAP2
 *		  PCSTS_TRAP1
 *	the following bits may be read by the user but not written.  only 
 *	hardware can change the value of the bit.  user writes to this bit 
 *	are ignored:
 *		  PCSTS_P_CASHE_HIT
 *		  PCSTS_TAG_PARITY_ERROR
 *		  PCSTS_DAL_DATA_PARITY_ERROR
 *		  PCSTS_P_DATA_PARITY_ERROR
 *		  PCSTS_BUS_ERROR
 *		  PCSTS_B_CASHE_HIT
 */
#define	PCSTS_FORCE_HIT			0x0001
#define	PCSTS_ENABLE_PTS		0x0002
#define	PCSTS_FLUSH_CASHE		0x0004
#define	PCSTS_ENABEL_REFRESH		0x0008  /* XRP only */
#define	PCSTS_P_CASHE_HIT		0x0010
#define	PCSTS_INTERRUPT			0x0020
#define	PCSTS_TRAP2			0x0040
#define	PCSTS_TRAP1			0x0080
#define	PCSTS_TAG_PARITY_ERROR		0x0100
#define	PCSTS_DAL_DATA_PARITY_ERROR	0x0200
#define	PCSTS_P_DATA_PARITY_ERROR	0x0400
#define	PCSTS_BUS_ERROR			0x0800
#define	PCSTS_B_CASHE_HIT		0x1000

/*
 * XRP only!
 *
 * Bits within the Rigel VAX6000-4xx REXMI Control And Status Register (RCSR)
 * (as defined in the XRP CPU spec rev 1.0)
 *	the following bits may be read or written by the user or the
 *	hardware (M):
 *		RCSR_WBD
 *		RCSR_ARD
 *		RCSR_ESI
 *		RCSR_IPID
 *		RCSR_TOS
 *		RCSR_RAM_SPD
 *		RCSR_CRDID
 *		RCSR_CCID
 *		RCSR_BPD
 *		RCSR_BP
 *		RCSR_LOCKOUT
 *		RCSR_LTS
 *		RCSR_RSSC_IPL
 *		RCSR_WD
 *	the following bits may be read or written by the user.  writing a '1' 
 *	to this bit will clear the bit.  writing a '0' to this bit has no 
 *	effect on the bit.  the hardware may read or write this bit (WC):
 *		RCSR_CNAKR
 *		RCSR_UWP
 *		RCSR_CFE
 *		RCSR_WDPE
 *		RCSR_XDP0PE
 *		RCSR_XDP1PE
 *		RCSR_XCAPE
 *	the following bits may be read by the user but not written.  only 
 *	hardware can change the value of the bit.  user writes to this bit 
 *	are ignored (RO):
 *		RCSR_XCA_REV
 *		RCSR_WS
 */
#define	RCSR_XCA_REV	0x0000000f	/* RO - XCA REV */
#define	RCSR_WBD	0x00000100	/* M - Write Buffer Disable */
#define	RCSR_ARD	0x00000200	/* M - Auto Retry Disable */
#define	RCSR_ESI	0x00000400	/* M - Enable Self Invalidates */
#define	RCSR_IPID	0x00000800	/* M - IP Interrupt Disable */
#define	RCSR_TOS	0x00001000	/* M - Timeout Select */
#define	RCSR_RAM_SPD	0x00002000	/* M - Ram Speed */
#define	RCSR_CRDID	0x00004000	/* M - CRD Interrupt Disable */
#define	RCSR_CCID	0x00003000	/* M - CC Interrupt Disable */
#define	RCSR_WS		0x00010000	/* RO - WARM Start */
#define	RCSR_BPD	0x00020000	/* M - Boot Processor Disable */
#define	RCSR_BP		0x00040000	/* M - Boot Processor */
#define	RCSR_CNAKR	0x00080000	/* WC - Commander NoAck Received */
#define	RCSR_UWP	0x00100000	/* WC - Unlock Write Pending */
#define	RCSR_LOCKOUT	0x00600000	/* M - (two bits) LOCKOUT */
#define	RCSR_LTS	0x00800000	/* M - Lockout Time Select */
#define	RCSR_RSSC_IPL	0x03000000	/* M - (two bits) RSSC IPL<1:0> */
#define	RCSR_WD		0x04000000	/* M - Write Disable */
#define	RCSR_CFE	0x08000000	/* WC - Cache Fill Error */
#define	RCSR_WDPE	0x10000000	/* WC - Write Data Parity Error */
#define	RCSR_XDP0PE	0x20000000	/* WC - XDP0 Parity Error */
#define	RCSR_XDP1PE	0x40000000	/* WC - XDP1 Parity Error */
#define	RCSR_XCAPE	0x80000000	/* WC - XCA Parity Error */

/*