ka6200.c

<B>Digital的Unix操作系统VAX 4.2源码</B>

		xma_pkg->xma_tmoer = xma2->xma_tmoer;
     		EVALID(elrp);
	}
	/* print to console if HIGH priority */
	if (priority < EL_PRILOW) {
		cprintf("Memory error \n");
		cprintf("xma_phys = %x\n",svtophy(xma2));
		cprintf("xma_type = %x\n",xma2->xma_type);
		cprintf("xma_xbe = %x\n",xma2->xma_xbe);
		cprintf("xma_seadr = %x\n",xma2->xma_seadr);
		cprintf("xma_mctl1 = %x\n",xma2->xma_mctl1);
		cprintf("xma_mecer = %x\n",xma2->xma_mecer);
		cprintf("xma_mecea = %x\n",xma2->xma_mecea);
		cprintf("xma_mctl2 = %x\n",xma2->xma_mctl2);
		cprintf("xma_becer = %x\n", xma2->xma_becer);
		cprintf("xma_becea = %x\n", xma2->xma_becea);
		cprintf("xma_stadr = %x\n", xma2->xma_stadr);
		cprintf("xma_enadr = %x\n", xma2->xma_enadr);
		cprintf("xma_intlv = %x\n", xma2->xma_intlv);
		cprintf("xma_mctl3 = %x\n", xma2->xma_mctl3);
		cprintf("xma_mctl4 = %x\n", xma2->xma_mctl4);
		cprintf("xma_bsctl = %x\n", xma2->xma_bsctl);
		cprintf("xma_bsadr = %x\n", xma2->xma_bsadr);
		cprintf("xma_eectl = %x\n", xma2->xma_eectl);
		cprintf("xma_tmoer = %x\n", xma2->xma_tmoer);
	}
}

/*
 *  ka6200crderr() --- "Soft" errors are reported through SCB vector
 *  0x54, at IPL 0x1a.  These errors include the following:
 *  This routine runs on the interrupt stack.
 *
 *		XBE:CRD    - Correctable main memory errors.
 *
 * 	2nd Level cache errors.
 *		CSR2:VBPE  - Valid bit parity error.
 *		CSR2:TPE   - Tag parity error.
 *		CSR2:IQO   - Invailidate Queue Overflow.
 *		CSR2:DTPE  - Duplicate Tag Store Parity Error.
 *		CSR2:CFE   - Cache Fill Error.,
 *		
 *	XMI soft errors.
 *		XBE:CC	   - Corrected conformation Errors.
 *		XBE:IPE    - Inconsistent Parity Error.
 *		XBE:PE	   - Parity Error.
 */

ka6200crderr()
{
	struct xcp_reg *xcp_node;
	int save_led_val;
	register struct xmidata *xmidata ;
	int node;
	struct xcp_machdep_data *xcpdata;

	register struct el_xcpsoft *sptr;
	register int csr2_errs,xbe_errs, flush_cache=0;

	xmidata = get_xmi(0);
	node = v6200csr->csr1 &0xf;

	xcpdata = (struct xcp_machdep_data *) CURRENT_CPUDATA->cpu_machdep;

	sptr = &xcpdata->xcpsoft;


	xcp_node =(struct xcp_reg *)xmidata->xmivirt+(v6200csr->csr1 & 0xf);
	
	csr2_errs = xcp_node->xcp_csr2;
	xbe_errs = xcp_node->xcp_xbe;

	xcp_node->xcp_csr2 = xcp_node->xcp_csr2;
	xcp_node->xcp_xbe = xcp_node->xcp_xbe;

	/* test for IQO error -- count and dismiss */
	if (csr2_errs & CSR2_IQO) {
		if (sptr)
			sptr->xcp_iqo++;
		flush_cache++;
	} 

	/* test for cache error */
	if (csr2_errs&(CSR2_VBPE|CSR2_TPE|CSR2_CFE|CSR2_DTPE)) {
		if (sptr) {
			if (csr2_errs & CSR2_VBPE) sptr->xcp_vbpe++;
			if (csr2_errs & CSR2_TPE) sptr->xcp_tpe++;
			if (csr2_errs & CSR2_CFE) sptr->xcp_cfe++;
			if (csr2_errs & CSR2_DTPE) sptr->xcp_dtpe++;
			if (CURRENT_CPUDATA->cpu_state & CPU_SOFT_DISABLE==0)
				xcp_log_soft(xcp_node,sptr);
		}
		flush_cache++;
	}

    	/* test for XMI error */
	if (xbe_errs & (XMI_CC|XMI_IPE|XMI_PE)) {

		if (sptr) {
			if (xbe_errs & XMI_CC) sptr->xcp_cc++;
			if (xbe_errs & XMI_IPE) sptr->xcp_ipe++;
			if (xbe_errs & XMI_PE) sptr->xcp_pe++;
			if (CURRENT_CPUDATA->cpu_state& CPU_SOFT_DISABLE==0)
				xcp_log_soft(xcp_node,sptr);
		}
		flush_cache++;
	} 

	/* test for CRD error */
	if (xbe_errs & (XMI_CRD)) 
		xma_check_crd(xcp_node,xmidata);

	if (flush_cache) {
		/* now enable cache by method specified in XCP spec */
		save_led_val = v6200csr->csr1 & 0x1ffff;  /* save led values */
		v6200csr->csr1 = 0x00040000|save_led_val; /* force miss */
		v6200csr->csr1 = 0x00140000|save_led_val; /* invalidate */
		v6200csr->csr1 = 0|save_led_val;	  /* enable cache */
	}
	return(0);
}

/*
 *	Routine xcp_log_soft
 *
 *	Discription:  This routine logs a soft error for processor pointed
 *	to by the pointer xcp_node.  A maximum of 1 packet are logged every
 * 	15 minutes.
 *
 */

xcp_log_soft(xcp_node,sptr) 
	struct xcp_reg *xcp_node;
	register struct el_xcpsoft *sptr;

{
	struct el_rec *elrp;
	register struct el_xcp54 *ptr;

	elrp = ealloc(sizeof(struct el_xma),EL_PRILOW);
	if (elrp) {
		LSUBID(elrp,ELCT_6200_INT54,EL_UNDEF,EL_UNDEF,EL_UNDEF,EL_UNDEF,EL_UNDEF);
		ptr = &elrp->el_body.el_xcp54;
		ptr->xcp_csr1 = v6200csr->csr1;
		ptr->xcp_cadr = mfpr(CADR);
		ptr->xcp_mser = mfpr(MSER);
		ptr->xcp_dtype = xcp_node->xcp_dtype;	
		ptr->xcp_xbe = xcp_node->xcp_xbe;	
		ptr->xcp_fadr = xcp_node->xcp_fadr;	
		ptr->xcp_gpr = xcp_node->xcp_csr2;	
		ptr->xcp_csr2 = xcp_node->xcp_csr2;
		ptr->xcp_soft = *sptr;
	
    		EVALID(elrp);	
	}
	else mprintf("log failed\n");


	CURRENT_CPUDATA->cpu_state|= CPU_SOFT_DISABLE;

}


/*
 *	Routine:	xma_check_crd
 *
 *	Discription:	This routine scans all of the Calypso arrays
 *	looking for the board that signaled the CRD error.  When found
 *	the error is logged and CRD's are disabled from that board.
 */
xma_check_crd(xcp,xmidata) 
	struct xcp_reg *xcp;
	struct xmidata *xmidata;
{
	int xminode;
	struct xma_reg *xma;

	xma = (struct xma_reg *) xmidata->xmivirt;
	for(xminode = 0; xminode < MAX_XMI_NODE; xminode++,xma++) {

		/* if node present then check to see if it is an 
		   XMA */
		if ((xmidata->xminodes_alive & (1<<xminode)) &&
		   ((short) (xma->xma_type) == XMI_XMA)) {

	   		/* check for CRD error and check that CRD 
			   logging for board has not been disabled */
			if ((xma->xma_mecer&(XMA_ECC_CRD_ERROR)) && 
			   ((xma->xma_mctl1&XMA_CTL1_CRD_DISABLE)==0)){
				/* log error */
				log_mem_error(xcp,xma,EL_PRILOW);

				/* clear CRD request */
				xma->xma_mecer = XMA_ECC_CRD_ERROR;
		
				/* disable further CRD's */
				xma->xma_mctl1|=(XMA_CTL1_CRD_DISABLE);
			}

		}
	}	
}



/*
 * Memenable enables the memory controller corrected data reporting.
 * This runs at regular intervals, turning on the interrupt.
 * The interrupt is turned off, per memory controller, when error
 * reporting occurs.  Thus we report at most once per memintvl.
 */

ka6200memenable ()
{
	int xminode;
	struct xmi_reg	*nxv;	/* virtual pointer to XMI node */
	struct xmidata *xmidata;

	xmidata = get_xmi(0);

	nxv = xmidata->xmivirt;
	for(xminode = 0; xminode < MAX_XMI_NODE; xminode++,nxv++) {
		if ((xmidata->xminodes_alive & (1<<xminode)) &&
		    ((short) (nxv->xmi_dtype) == XMI_XMA)) {
	
			/* clear disable CRD flag in memory controller */
			((struct xma_reg *)nxv)->xma_mctl1 
					      &= ~(XMA_CTL1_CRD_DISABLE);
		}
	}
	return(0);

}

/*
 * this routine sets the cache to the state passed.  enabled/disabled
 */

ka6200setcache(state)
int state;

{
  	if (state) {
		/* enable the cache */
		ka6200_enable_cache();
		return(0);
	}
}

ka6200cachenbl()
{
	cache_state = 0x1;
	return(0);
}


ka6200tocons(c)
	register int c;
{
	register int timeo;

	timeo = 100000;
	while ((mfpr (TXCS) & TXCS_RDY) == 0) {
		if (timeo-- <= 0) {
			return(0);
		}
	}
	mtpr (TXDB, c);
	return(0);
}

int ka6200badaddr(addr,len)
caddr_t addr;
int len;
{
	register int foo,s,i;	
	register struct bi_nodespace *biptr;
	
#ifdef lint
	len=len;
#endif lint

	s=spl7();

	for (i=0; i < nNVAXBI ; i++) {
		if (biptr = bidata[i].cpu_biic_addr) {
			biptr->biic.biic_err = biptr->biic.biic_err;
			foo = biptr->biic.biic_gpr0;
		}
	}

	foo = bbadaddr(addr,len);


	for (i=0; i < nNVAXBI ; i++) {
		if (biptr = bidata[i].cpu_biic_addr) {
			if ((biptr->biic.biic_err 
				& ~BIERR_UPEN)!=0) foo=1;
			biptr->biic.biic_err = biptr->biic.biic_err;
		}
	}

	splx(s);
	return(foo);
}


/* reboot VAX62xx machine */
ka6200reboot() {

	struct xmidata *xmidata;
	struct xcp_reg *xcp_node;


	/* set O/S reboot flag so reboot happens */
	ccabase.cca_hflag |=CCA_V_REBOOT;
	
	/* get pointer to xcp node to reboot*/
	xmidata = get_xmi(0);
	xcp_node =(struct xcp_reg *)xmidata->xmivirt+(v6200csr->csr1 & 0xf);
	
	/* hit the halt bit... so long */
	xcp_node->xcp_xbe = (xcp_node->xcp_xbe & ~XMI_XBAD) | XMI_NHALT;

	DELAY(10000);	/* give time for the "XMI_NHALT" to work */
	
	/* just in case "XMI_NHALT" doesn't work. We should never reach
	   the halt */
	asm("halt");  
}

/* halt VAX62xx machine at console */
ka6200halt() {


	struct xmidata *xmidata;
	struct xcp_reg *xcp_node;

	/* get pointer to xcp node that machine checked */
	xmidata = get_xmi(0);
	xcp_node =(struct xcp_reg *)xmidata->xmivirt+(v6200csr->csr1 & 0xf);

	/* hit the halt bit... so long */
	xcp_node->xcp_xbe = (xcp_node->xcp_xbe & ~XMI_XBAD) | XMI_NHALT;

	DELAY(10000);	/* give time for the "XMI_NHALT" to work */
	
	/* just in case "XMI_NHALT" doesn't work. We should never reach
	   the halt */
	asm("halt");  
}

xcpinit(nxv,nxp,xminumber,xminode)
char *nxv;
char *nxp;
int xminumber,xminode;
{
#ifdef lint
	nxv=nxv; nxp=nxp;
	xminumber=xminumber;
	xminode = xminode;
#endif lint


}

ka6200nexaddr(xminumber,xminode) 
 	int xminode,xminumber;
{
	return((XMI_START_PHYS+(xminode * 0x80000)));		
}

ka6200umaddr(binumber,binode) 
 	int binumber,binode;
{

	return(((int) bidata[binumber].biphys)  
		+ 0x400000 + (0x40000 * binode));

}

ka6200udevaddr(binumber,binode) 
 	int binumber,binode;
{
	return(((int) bidata[binumber].biphys)  
		+ 0x400000 + 0x3e000 + (0x40000 * binode));
}