📄 vaxfloat.s
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.word 0f - 1b # 3afd .word 0f - 1b # 3bfd .word 0f - 1b # 3cfd .word 0f - 1b # 3dfd .word 0f - 1b # 3efd .word 0f - 1b # 3ffd .word inst_addg2-1b # 40fd addg2 .word inst_addg3-1b # 41fd addg3 .word inst_subg2-1b # 42fd subg2 .word inst_subg3-1b # 43fd subg3 .word inst_mulg2-1b # 44fd mulg2 .word inst_mulg3-1b # 45fd mulg3 .word inst_divg2-1b # 46fd divg2 .word inst_divg3-1b # 47fd divg3 .word inst_cvtgb-1b # 48fd cvtgb .word inst_cvtgw-1b # 49fd cvtgw .word inst_cvtgl-1b # 4afd cvtgl .word inst_cvtrgl-1b # 4bfd cvtrgl .word inst_cvtbg-1b # 4cfd cvtbg .word inst_cvtwg-1b # 4dfd cvtwg .word inst_cvtlg-1b # 4efd cvtlg .word inst_acbg-1b # 4ffd acbg .word inst_movg-1b # 50fd movg .word inst_cmpg-1b # 51fd cmpg .word inst_mnegg-1b # 52fd mnegg .word inst_tstg-1b # 53fd tstg .word inst_emodg-1b # 54fd emodg .word inst_polyg-1b # 55fd polyg .word inst_cvtgh-1b # 56fd cvtgh .word 0f - 1b # 57fd .word 0f - 1b # 58fd .word 0f - 1b # 59fd .word 0f - 1b # 5afd .word 0f - 1b # 5bfd .word 0f - 1b # 5cfd .word 0f - 1b # 5dfd .word 0f - 1b # 5efd .word 0f - 1b # 5ffd .word inst_addh2-1b # 60fd addh2 .word inst_addh3-1b # 61fd addh3 .word inst_subh2-1b # 62fd subh2 .word inst_subh3-1b # 63fd subh3 .word inst_mulh2-1b # 64fd mulh2 .word inst_mulh3-1b # 65fd mulh3 .word inst_divh2-1b # 66fd divh2 .word inst_divh3-1b # 67fd divh3 .word inst_cvthb-1b # 68fd cvthb .word inst_cvthw-1b # 69fd cvthw .word inst_cvthl-1b # 6afd cvthl .word inst_cvtrhl-1b # 6bfd cvtrhl .word inst_cvtbh-1b # 6cfd cvtbh .word inst_cvtwh-1b # 6dfd cvtwh .word inst_cvtlh-1b # 6efd cvtlh .word inst_acbh-1b # 6ffd acbh .word inst_movh-1b # 70fd movh .word inst_cmph-1b # 71fd cmph .word inst_mnegh-1b # 72fd mnegh .word inst_tsth-1b # 73fd tsth .word inst_emodh-1b # 74fd emodh .word inst_polyh-1b # 75fd polyh .word inst_cvthg-1b # 76fd cvthg .word 0f - 1b # 77fd .word 0f - 1b # 78fd .word 0f - 1b # 79fd .word 0f - 1b # 7afd .word 0f - 1b # 7bfd .word inst_clro-1b # 7cfd clro,clrh .word inst_movo-1b # 7dfd movo .word inst_movao-1b # 7efd movao,movah .word inst_pushao-1b # 7ffd pushao,pushah 0: cmpb r0,$0x99 # cvtfg? bgtru 3f # skip if not beql 5f # skip if yes cmpb r0,$0x98 # cvtfh? bneq 9f # error if not brw inst_cvtfh # execute cvtfh 5: brw inst_cvtfg # execute cvtfg 3: cmpb r0,$0xf6 # cvthf? bgtru 4f # skip if not bneq 9f # error if lssu brw inst_cvthf # execute cvthf 4: cmpb r0,$0xf7 # cvthd? bneq 9f # error if not brw inst_cvthd # execute cvthd 9: brw opcode_fault # shouldn't happen # # normal_exit - normal end of instruction emulation # # entered by branching # # no parameters # # discussion # # this routine restores control to the user program whenever # the emulation ends without causing an exception. first the v # and iv bits in the user's psl are checked. if they are both # set then an integer overflow trap is signaled. when the # emulator returns, all of the registers, pc, and the psl are # set to the emulated values. # # the method of leaving the emulator consists of pushing the # user's pc and psl onto the user's stack putting the saved ap # and fp back in their proper places in the frame and performing # the indicated adjustment so that when a ret instruction is # executed all of the registers up to fp will be restored and # the stack pointer will be positioned to the pc, psl pair. # # at this point, a speed optimization is performed. if the # next instruction is also one we emulate, then we can bypass the # overhead for the reserved opcode fault and exception # dispatching by merely looping back to the beginning of the # emulator. after the ret restores all registers, the stack # contains the pc/psl pair for the next instruction. the psl is # examined to see if the t-bit is set. if so, we can't do the # optimization. if t is clear, we then examine the next opcode. # if it is one which we emulate, a branch is made to emulate$ # to begin emulation of the next instruction. note that the # "arguments" to emulate$, a pc/psl pair, are already in place! # # if the optimization can not be performed, an rei is executed # which restores the pc and psl for the next instruction. # normal_exit: # entrance bbc $psl_v,psl(fp),1f # no integer overflow - bypass bbc $psl_iv,psl(fp),1f # no integer overflow trap - skip brw int_overflow # process the integer overflow trap 1: movab short_local(fp),sp # shorten the frame movl $8,r0 # r0 = size of pc, psl pair bsbw test_frame # make sure we have room to push it subl2 $8,reg_sp(fp) # allocate room on the user's stack movq reg_pc(fp),*reg_sp(fp) # push the pc, psl pair movq reg_ap(fp),save_ap(fp) # put the user's pc, psl pair back movab 2f,save_pc(fp) # store our return point movab frame_end+4(fp),r0 # r0 = location of end of frame subl3 r0,reg_sp(fp),r1 # r1 = distance of user sp from it extzv $0,$2,r1,r2 # r2 = stack alignment insv r2,$mask_align,$2,save_mask(fp) # store it into the frame addl2 r2,r0 # compute the parameter area location ashl $-2,r1,-4(r0) # store the parameter count ret # return (to next instruction) #+ # perform instruction lookahead for speed optimization. # at this point, 0(sp) contains the pc of the next user instruction, 4(sp) # has the user psl. #- 2: brb 9f /* * I commented this code out so that it would not try to decode the * next instruction. The reason for this is that an array must * be initialized to indicated what instructions can be * decoded based on the machine's architecture. Maybe someday we * will do this. * * bbs $psl_t, 4(sp), 9f # if t-bit set, don't do lookahead * movq r0, -(sp) # save r0-r1 temporarily * movl 8(sp), r1 # get pc in r1 * extzv $psl_cam, $2, 12(sp), r0# get current access mode in r0 * prober r0, $2, (r1) # can we read the next two bytes? * beql 8f # if not, just return * movzbl (r1)+, r0 # get next opcode byte in r0 * cmpb r0, $0xfd # 2-byte opcode? * beql 0f # skip if yes * cmpb r0, $0x40 # compare against addf2 * blssu 8f # not emulated if lssu * cmpb r0, $0x76 # compare against cvtdf * bgtru 8f # not emulated if gtru * mull2 $4, r0 # get bit offset of mask * extzv r0, $4, inst_types_1byte, r1 # get inst-types mask in r1 * brb 7f # join common code *0: cvtbl (r1), r0 # get next opcode byte in r0 * blss 3f # skip if greater than pushao (0x7f) * cmpb r0, $0x32 # compare against cvtdh * blssu 8f # not emulated if lssu * mull2 $4, r0 # get bit offset of mask * extzv r0, $4, inst_types_2byte, r1 # get inst-types mask in r1 * brb 7f # join common code *8: movq (sp)+, r0 # restore saved r0 */ 9: rei # return to the next user instruction/* *3: movzbl $(it_f+it_h), r1 # assume cvtfh or cvthf * cmpb r0,$0x99 # compare against cvtfg * bgtru 4f # not cvtfg or cvtfh if gtru * cmpb r0,$0x98 # compare against cvtfh * blssu 8b # not emulated if lssu * beql 7f # r1 mask is correct for cvtfh * xorb2 $(it_g+it_h), r1 # cvtfg - switch to using f and g * brb 7f # join common code *4: cmpb r0, $0xf6 # compare against cvthf * blssu 8b # not emulated if lssu * beql 7f # join common code if cvthf * xorb2 $(it_f+it_d), r1 # cvthd - switch to using h and d *7: ashl $arc$v_dflt_emul, r1, r1# align mask with exe$gl_archflag * bitl r1, *$exe$gl_archflag # should we emulate this instruction? * beql 8b # if all bits test zero, no * movq (sp)+, r0 # pop saved r0 and r1 * jmp vax$$emulate_fp # emulate the next instruction */ # assume arc$v_fflt_emul eq arc$v_dflt_emul+1 # assume arc$v_gflt_emul eq arc$v_fflt_emul+1 # assume arc$v_hflt_emul eq arc$v_gflt_emul+1 # #+ # the following two tables provide information on what floating types # are manipulated by each instruction. for each opcode there are # four bits which, if set, indicate that the instruction uses d, f, g # and h_floating data, respectively. these four bits are compared against # the corresponding four bits in exe$gl_archflag to see if the next # instruction should be emulated; this test takes place in normal_exit. #- #+ # macro inst_type generates table entries #- # .macro inst_type opcode1,opcode2 # $$x=0 # .irpc $$t,<opcode2> # $$x=$$x+it_'$$t' # .endr # $$x=$$x@4 # .irpc $$t,<opcode1> # $$x=$$x+it_'$$t' # .endr # .byte $$x # .endm #+ # inst_types_1byte - masks for 1-byte instructions. # covers opcodes 40 (addf2) through 76 (cvtdf) #- # inst_types_1byte=.-(0x40/2) # offset for first opcode.set inst_types_1byte,0x277 # inst_type f,f # addf2, addf3.byte 0x22 # inst_type f,f # subf2, subf3.byte 0x22 # inst_type f,f # mulf2, mulf3.byte 0x22 # inst_type f,f # divf2, divf3.byte 0x22 # inst_type f,f # cvtfb, cvtfw.byte 0x22 # inst_type f,f # cvtfl, cvtrfl.byte 0x22 # inst_type f,f # cvtbf, cvtwf.byte 0x22 # inst_type f,f # cvtlf, acbf.byte 0x22 # inst_type f,f # movf, cmpf.byte 0x22 # inst_type f,f # mnegf, tstf.byte 0x22 # inst_type f,f # emodf, polyf.byte 0x22 # inst_type fd,x # cvtfd, <57>.byte 0x3 # inst_type x,x # adawi, <59>.byte 0x0 # inst_type x,x # <5a>, <5b>.byte 0x0 # inst_type x,x # insqhi, insqti.byte 0x0 # inst_type x,x # remqhi, remqti.byte 0x0 # inst_type d,d # addd2, addd3.byte 0x11 # inst_type d,d # subd2, subd3.byte 0x11 # inst_type d,d # muld2, muld3.byte 0x11 # inst_type d,d # divd2, divd3.byte 0x11 # inst_type d,d # cvtdb, cvtdw.byte 0x11 # inst_type d,d # cvtdl, cvtrdl.byte 0x11 # inst_type d,d # cvtbd, cvtwd.byte 0x11 # inst_type d,d # cvtld, acbd.byte 0x11 # inst_type d,d # movd, cmpd.byte 0x11 # inst_type d,d # mnegd, tstd.byte 0x11 # inst_type d,d # emodd, polyd.byte 0x11 # inst_type fd,x # cvtdf, <77>.byte 0x3 #+ # inst_types_2byte - masks for 2-byte instructions. # covers opcodes 32fd (cvtdh) through 7ffd (pushao) #- # inst_types_2byte=.-(0x32/2) # offset for first opcode.set inst_types_2byte,0x29a # inst_type dh,gf # cvtdh, cvtgf.byte 0x69 # inst_type x,x # <34fd>, <35fd>.byte 0x0 # inst_type x,x # <36fd>, <37fd>.byte 0x0 # inst_type x,x # <38fd>, <39fd>.byte 0x0 # inst_type x,x # <3afd>, <3bfd>.byte 0x0 # inst_type x,x # <3cfd>, <3dfd>.byte 0x0 # inst_type x,x # <3efd>, <3ffd>.byte 0x0 # inst_type g,g # addg2, addg3.byte 0x44 # inst_type g,g # subg2, subg3.byte 0x44 # inst_type g,g # mulg2, mulg3.byte 0x44 # inst_type g,g # divg2, divg3.byte 0x44 # inst_type g,g # cvtgb, cvtgw.byte 0x44 # inst_type g,g # cvtgl, cvtrgl.byte 0x44 # inst_type g,g # cvtbg, cvtwg.byte 0x44 # inst_type g,g # cvtlg, acbg.byte 0x44 # inst_type g,g # movg, cmpg.byte 0x44 # inst_type g,g # mnegg, tstg.byte 0x44 # inst_type g,g # emodg, polyg.byte 0x44 # inst_type gh,x # cvtgh, <57fd>.byte 0xc # inst_type x,x # <58fd>, <59fd>.byte 0x0 # inst_type x,x # <5afd>, <5bfd>.byte 0x0 # inst_type x,x # <5cfd>, <5dfd>.byte 0x0 # inst_type x,x # <5efd>, <5ffd>.byte 0x0 # inst_type h,h # addh2, addh3.byte 0x88 # inst_type h,h # subh2, subh3.byte 0x88 # inst_type h,h # mulh2, mulh3.byte 0x88 # inst_type h,h # divh2, divh3.byte 0x88 # inst_type h,h # cvthb, cvthw.byte 0x88 # inst_type h,h # cvthl, cvtrhl.byte 0x88 # inst_type h,h # cvtbh, cvtwh.byte 0x88 # inst_type h,h # cvtlh, acbh.byte 0x88 # inst_type h,h # movh, cmph.byte 0x88 # inst_type h,h # mnegh, tsth.byte 0x88 # inst_type h,h # emodh, polyh.byte 0x88 # inst_type hg,x # cvthg, <77fd>.byte 0xc # inst_type x,x # <78fd>, <79fd>.byte 0x0 # inst_type x,x # <7afd>, <7bfd>.byte 0x0 # inst_type h,h # clro, movo.byte 0x88 # inst_type h,h # movao, pushao.byte 0x88 # # test_frame - test frame location and move if necessary # # entered by subroutine branching # # parameter: r0 = size of information to be pushed # # returns with r0 = distance frame was moved # # discussion # # this routine determines whether or not the address given # by subtracting r0 from the user's stack pointer can be made # the location following a parameter list without the location # being within the local storage. if this cannot be done then # the entire procedure frame is moved so the condition can be # satisfied. the distance that the procedure frame was moved # is returned in r0. the value is zero if the frame is not # moved. # # note: 1. the switch from one frame location to another is # performed by a single indivisible popr instruction # so the emulator is never in an anomalous state. #
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