usercopy.s

<B>Digital的Unix操作系统VAX 4.2源码</B>

	and	v0, 1		# low-order bit for align chk
	subu	v1, zero, a1	# -src
	bne	v0, zero, hbytecopy	# src and dst not alignable
	addu	t5, a1, a2	# firewall panic on overrun

/*
 * src and dst can be simultaneously word aligned.
 */
	and	v1, 3		# number of bytes til aligned
	subu	a2, v1		# bcount -= alignment
	addu	a3,v1,a0	# end of align move
	beq	v1, zero, blkcpin	# already aligned

/*
 * This is the easy way, could maybe be done better.  The problem
 * is that lwl/r and swl/r will not work on the 16 bit side.  Since
 * worst case is three times through, the math to do the possible
 * half-word copy does not seem worth it, nor does the shifting to
 * use the lwl/r from the 32 bit side.
 */
1:
	lb	v0, 0(a0)
	addu	a0, 1
	sb	v0, 0(a1)
	addu	a1, 1		# should go in the BDSLOT
	bne	a0, a3, 1b
	
/* 16 byte block copy */

blkcpin:
	and	a3, a2, ~15	# total space in 16 byte chunks
	subu	a2, a3		# count after by-16 byte loop done
	beq	a3, zero, hwordcopy	# less than 16 bytes to copy
	addu	a3, a0		# source endpoint
	.set noreorder
1:	
	lhu	v0, 0(a0)
	addu	a0, 16
	lhu	v1, -14(a0)
	sll	v0, 16
	lhu	t0, -12(a0)
	or	v0, v1
	sw	v0, 0(a1)
	lhu	t1, -10(a0)
	sll	t0, 16
	or	t0, t1
	lhu	v0, -8(a0)
	sw	t0, 4(a1)
	lhu	v1, -6(a0)
	sll	v0, 16
	or	v0, v1
	lhu	t0, -4(a0)
	sw	v0, 8(a1)
	lhu	t1, -2(a0)
	sll	t0, 16
	or	t0, t1
	sw	t0, 12(a1)
	bne	a0, a3, 1b
	addu	a1, 16			# dst+= 16; fills BD slot
	.set reorder
	bgt	a1, t5, bad
	b	hwordcopy
panic_lab:
	.data
	.asciiz "hwcpin"
	.text
bad:
	lw	a0, panic_lab
	jal	panic
	
	END(hwcpin)
#endif oldmips

/*
 * The following routines uload_word(), uload_half(), uloaduhalf(),
 * ustore_word() and ustore_half() load and store unaligned items.
 * The "addr" parameter is the address at which the reference is to be
 * made.  For load routines the value is returned indirectly through
 * the "pword" parameter.  For store routines the "value" pramameter
 * is stored.  All routines indicate an error by returning a non-zero
 * value.  If no error occurs a zero is returned.
 */

/*
 * int uload_word(addr, pword)
 * u_int addr, *pword;
 */
LEAF(uload_word)
#ifdef ASSERTIONS
	lw	v0,u+PCB_CPUPTR
	lw	v0,CPU_NOFAULT(v0)
	beq	v0,zero,8f
	PANIC("recursive nofault")
8:
#endif ASSERTIONS
	.set	noreorder
	lw	v0,u+PCB_CPUPTR
	li	v1,NF_FIXADE		# LDSLOT
	sw	v1,CPU_NOFAULT(v0)
	ulw	v1,0(a0)
	sw	zero,CPU_NOFAULT(v0)
	.set	reorder
	sw	v1,0(a1)
	move	v0,zero
	j	ra
	END(uload_word)

/*
 * int uload_half(addr, pword)
 * u_int addr, *pword;
 */
LEAF(uload_half)
#ifdef ASSERTIONS
	lw	v0,u+PCB_CPUPTR
	lw	v0,CPU_NOFAULT(v0)
	beq	v0,zero,8f
	PANIC("recursive nofault")
8:
#endif ASSERTIONS
	.set	noreorder
	lw	v0,u+PCB_CPUPTR
	li	v1,NF_FIXADE		#LDSLOT
	sw	v1,CPU_NOFAULT(v0)
	.set	reorder
	ulh	v1,0(a0)
	.set	noreorder
	sw	zero,CPU_NOFAULT(v0)
	.set	reorder
	sw	v1,0(a1)
	move	v0,zero
	j	ra
	END(uload_half)

/*
 * int uload_uhalf(addr, pword)
 * u_int addr, *pword;
 */
LEAF(uload_uhalf)
#ifdef ASSERTIONS
	lw	v0,u+PCB_CPUPTR
	lw	v0,CPU_NOFAULT(v0)
	beq	v0,zero,8f
	PANIC("recursive nofault")
8:
#endif ASSERTIONS
	lw	v0,u+PCB_CPUPTR
	li	v1,NF_FIXADE		#LDSLOT
	.set	noreorder
	sw	v1,CPU_NOFAULT(v0)
	.set	reorder
	ulhu	v1,0(a0)
	.set	noreorder
	sw	zero,CPU_NOFAULT(v0)
	.set	reorder
	sw	v1,0(a1)
	move	v0,zero
	j	ra
	END(uload_uhalf)

/*
 * ustore_word(addr, value)
 * u_int addr, value;
 */
LEAF(ustore_word)
#ifdef ASSERTIONS
	lw	v0,u+PCB_CPUPTR
	lw	v0,CPU_NOFAULT(v0)
	beq	v0,zero,8f
	PANIC("recursive nofault")
8:
#endif ASSERTIONS
	lw	v1,u+PCB_CPUPTR
	li	v0,NF_FIXADE		# LDSLOT
	.set	noreorder
	sw	v0,CPU_NOFAULT(v1)
	usw	a1,0(a0)
	sw	zero,CPU_NOFAULT(v1)
	.set	reorder
	move	v0,zero
	j	ra
	END(ustore_word)

/*
 * ustore_half(addr, value)
 * u_int addr, value;
 */
LEAF(ustore_half)
#ifdef ASSERTIONS
	lw	v0,u+PCB_CPUPTR
	lw	v0,CPU_NOFAULT(v0)
	beq	v0,zero,8f
	PANIC("recursive nofault")
8:
#endif ASSERTIONS
	lw	v1,u+PCB_CPUPTR
	li	v0,NF_FIXADE		#LDSLOT
	.set	noreorder
	sw	v0,CPU_NOFAULT(v1)
	ush	a1,0(a0)
	sw	zero,CPU_NOFAULT(v1)
	.set	reorder
	move	v0,zero
	j	ra
	END(ustore_half)

LEAF(fixade_error)
	move	v0,gp
	j	ra
	END(fixade_error)

/* isis */

/*
 * kn5800_cln_icache(addr, len, wbfladdr)
 * flush i cache for range of addr to addr+len-1
 * MUST NOT DESTROY a0 AND a1, SEE clean_cache ABOVE
 * wbfladdr is the address to read to cause a write buffer flush
 */
LEAF(kn5800_cln_icache)
	lw	t1,icache_size
	.set noreorder
	nop
	mfc0	t3,C0_SR		# save sr
	nop
	mtc0	zero,C0_SR		# interrupts off
	nop
	.set reorder

	.set	noreorder
	la	v0,1f
	or	v0,K1BASE
	j	v0			# run uncached
	nop
1:	lw	v0,0(a2)		# isis hack to flush write buffer
	nop
	li	v0,SR_ISC|SR_SWC	# disable intr, isolate and swap
	mtc0	v0,C0_SR
	bltu	t1,a1,1f		# cache is smaller than region
	nop
	move	t1,a1
1:	addu	t1,a0			# ending address + 1
	move	t0,a0
	la	v0,1f			# run cached
	j	v0
	nop
	.set	reorder

1:	sb	zero,0(t0)
	sb	zero,4(t0)
	sb	zero,8(t0)
	sb	zero,12(t0)
	sb	zero,16(t0)
	sb	zero,20(t0)
	sb	zero,24(t0)
	addu	t0,32
	sb	zero,-4(t0)
	bltu	t0,t1,1b

	.set	noreorder
	la	v0,1f
	or	v0,K1BASE
	j	v0			# run uncached
	nop

1:	nop				# insure isolated stores out of pipe
	mtc0	zero,C0_SR		# unisolate, unswap
	nop				# keep pipeline clean
	nop				# keep pipeline clean
	nop				# keep pipeline clean
	mtc0	t3,C0_SR		# enable interrupts
	j	ra			# return and run cached
	nop
	.set	reorder
	END(kn5800_cln_icache)

LEAF(kn5800_cln_dcache)
	lw	t2,dcache_size
	.set noreorder
	nop
	mfc0	t3,C0_SR		# save sr
	nop
	.set reorder

	.set	noreorder
	lw	v0,0(a2)		# isis hack - to flush write buffer
	li	v0,SR_ISC		# disable interrupts, isolate caches
	mtc0	v0,C0_SR
	bltu	t2,a1,1f		# cache is smaller than region
	nop
	move	t2,a1
1:	addu	t2,a0			# ending address + 1
	move	t0,a0
	nop
	nop				# cache must be isolated by now
	.set	reorder

1:	sb	zero,0(t0)
	sb	zero,4(t0)
	sb	zero,8(t0)
	sb	zero,12(t0)
	sb	zero,16(t0)
	sb	zero,20(t0)
	sb	zero,24(t0)
	addu	t0,32
	sb	zero,-4(t0)
	bltu	t0,t2,1b

	.set	noreorder
	nop				# insure isolated stores out of pipe
	nop
	nop
	mtc0	t3,C0_SR		# un-isolate, enable interrupts
	nop				# insure cache unisolated
	nop				# insure cache unisolated
	nop				# insure cache unisolated
	j	ra
	nop
	.set	reorder
	END(kn5800_cln_dcache)

/*
 * kn5800_flsh_cache()
 * flush entire cache
 */
LEAF(kn5800_flsh_cache)
	lw	t1,icache_size		# must load before isolating
	lw	t2,dcache_size		# must load before isolating
	.set noreorder
	nop
	mfc0	t3,C0_SR		# save SR
	nop
	mtc0	zero,C0_SR		# interrupts off
	nop
	.set reorder

	.set	noreorder
	la	v0,1f
	or	v0,K1BASE
	j	v0			# run uncached
	nop

	/*
	 * flush text cache - but for isis we must muck with the rinval
	 * bit in csr1 to stop invalidates.
	 */
	/* code added for isis (except for the label "1:" begins here. */
1:	lui	v1, 0x1			# put RINVAL bit in v1
	lw	t7, 0(a0)		# get csr1 contents
	nop
	or	t8, t7, v1		# set rinval bit in t8
	sw	t8, 0(a0)		# set RINVAL in csr1
	nop
2:	lw	t7, 0(a0)		# read csr1
	nop
	and	t8, t7, v1		# check rinval
	beq	t8,zero,2b		# loop till set
	nop				# branch delay slot
	/* end code added for isis */
	li	v0,SR_ISC|SR_SWC	# disable intr, isolate and swap
	mtc0	v0,C0_SR
	li	t0,K1BASE
	subu	t0,t1
	li	t1,K1BASE
	la	v0,1f			# run cached
	j	v0
	nop
	.set	reorder

1:	sb	zero,0(t0)
	sb	zero,4(t0)
	sb	zero,8(t0)
	sb	zero,12(t0)
	sb	zero,16(t0)
	sb	zero,20(t0)
	sb	zero,24(t0)
	addu	t0,32
	sb	zero,-4(t0)
	bne	t0,t1,1b

	.set	noreorder
	la	v0,1f
	or	v0,K1BASE
	j	v0			# run uncached
	nop

	/*
	 * flush data cache
	 */
1:	li	v0,SR_ISC		# isolate and swap back caches
	mtc0	v0,C0_SR
	li	t0,K1BASE
	subu	t0,t2
	la	v0,1f
	j	v0			# back to cached mode
	nop
	.set	reorder

1:	sb	zero,0(t0)
	sb	zero,4(t0)
	sb	zero,8(t0)
	sb	zero,12(t0)
	sb	zero,16(t0)
	sb	zero,20(t0)
	sb	zero,24(t0)
	addu	t0,32
	sb	zero,-4(t0)
	bne	t0,t1,1b

	.set	noreorder
	nop				# insure isolated stores out of pipe
	nop
	nop
	mtc0	t3,C0_SR		# un-isolate, enable interrupts
	nop				# insure cache unisolate
	nop
	nop
	nop
	.set	reorder
#ifdef CACHETRICKS
	lw	v0,icachemask		# index of last entry in icachecnt
	li	v1,0
	sll	v0,1			# offset to last entry
1:	lhu	t0,icachecnt(v1)
	addu	t0,1
	sh	t0,icachecnt(v1)
	addu	v1,2
	ble	v1,v0,1b		# more cachecnt's to bump

	lw	v0,dcachemask		# index of last entry in dcachecnt
	li	v1,0
	sll	v0,1			# offset to last entry
1:	lhu	t0,dcachecnt(v1)
	addu	t0,1
	sh	t0,dcachecnt(v1)
	addu	v1,2
	ble	v1,v0,1b		# more cachecnt's to bump
#endif CACHETRICKS

	j	ra
	END(kkn5800_flsh_cache)

/*
 * kn5800_page_iflush(addr, wbfladdr)
 * flush one page of i cache, addr is assumed to be in K0SEG
 * wbfladdr is the address to read to cause a write buffer flush
 */
LEAF(kn5800_pg_iflush)
	lw	t1,icache_size
	.set noreorder
	nop
	mfc0	t3,C0_SR		# save sr
	nop
	mtc0	zero,C0_SR		# interrupts off
	nop
	.set reorder
	.set	noreorder
	la	v0,1f
	or	v0,K1BASE
	j	v0			# run uncached
	nop				# BDSLOT

	/*
	 * flush text cache
	 */
1:	lw	v0,0(a1)		# isis hack to flush write buffer
	li	v0,SR_ISC|SR_SWC	# disable intr, isolate and swap
	mtc0	v0,C0_SR
	bltu	t1,NBPG,1f		# cache is smaller than region
	nop				# BDSLOT
	li	t1,NBPG
1:	addu	t1,a0			# ending address + 1
	move	t0,a0
	la	v0,1f			# run cached
	j	v0
	nop				# cache must be isolated by now
	.set	reorder

1:	sb	zero,0(t0)
	sb	zero,4(t0)
	sb	zero,8(t0)
	sb	zero,12(t0)
	sb	zero,16(t0)
	sb	zero,20(t0)
	sb	zero,24(t0)
	addu	t0,32
	sb	zero,-4(t0)
	bltu	t0,t1,1b

	.set	noreorder
	la	v0,1f
	or	v0,K1BASE
	j	v0			# run uncached
	nop

1:	nop				# insure isolated stores out of pipe
	mtc0	zero,C0_SR		# unisolate, unswap
	nop
	nop
	nop
	nop
	mtc0	t3,C0_SR		# enable interrupts
	la	v0,1f			# run cached
	j	v0
	nop

	.set	reorder
1:
#ifdef CACHETRICKS
	lw	v0,icachemask
	srl	t1,a0,PGSHIFT
	and	t1,v0
	sll	t1,1			# cachecnt index
	lhu	t0,icachecnt(t1)
	addu	t0,1
	sh	t0,icachecnt(t1)
#endif CACHETRICKS
	j	ra
	END(kn5800_pg_iflush)

/*
 * kn5800_page_dflush(addr, wbfladdr)
 * flush one page of i cache, addr is assumed to be in K0SEG
 * wbfladdr is the address to read to cause a write buffer flush
 */
LEAF(kn5800_pg_dflush)
	lw	t2,dcache_size
	.set noreorder
	nop
	mfc0	t3,C0_SR		# save sr
	nop
	.set reorder

	.set	noreorder
	lw	v0,0(a1)		# isis hack to flush write buffer
	li	v0,SR_ISC		# interrupts off, isolate caches
	mtc0	v0,C0_SR
	bltu	t2,NBPG,1f		# cache is smaller than region
	nop
	li	t2,NBPG
1:	addu	t2,a0			# ending address + 1
	move	t0,a0			# cache must be isolated by now
	.set	reorder

1:	sb	zero,0(t0)
	sb	zero,4(t0)
	sb	zero,8(t0)
	sb	zero,12(t0)
	sb	zero,16(t0)
	sb	zero,20(t0)
	sb	zero,24(t0)
	addu	t0,32
	sb	zero,-4(t0)
	bltu	t0,t2,1b

	.set	noreorder
	nop				# insure isolated stores out of pipe
	nop
	nop
	mtc0	t3,C0_SR		# un-isolate, enable interrupts
	nop				# insure cache unisolated
	nop
	nop
	.set	reorder
#ifdef CACHETRICKS
	lw	v0,dcachemask
	srl	t1,a0,PGSHIFT
	and	t1,v0
	sll	t1,1			# cachecnt index
	lhu	t0,dcachecnt(t1)
	addu	t0,1
	sh	t0,dcachecnt(t1)
#endif CACHETRICKS
	j	ra
	END(kkn5800_pg_dflush)