cpu.h

<B>Digital的Unix操作系统VAX 4.2源码</B>

/*
 * @(#)cpu.h	4.3	(ULTRIX)	9/4/90
 */
/************************************************************************
 *									*
 *			Copyright (c) 1988 by				*
 *		Digital Equipment Corporation, Maynard, MA		*
 *			All rights reserved.				*
 *									*
 *   This software is furnished under a license and may be used and	*
 *   copied  only  in accordance with the terms of such license and	*
 *   with the  inclusion  of  the  above  copyright  notice.   This	*
 *   software  or  any  other copies thereof may not be provided or	*
 *   otherwise made available to any other person.  No title to and	*
 *   ownership of the software is hereby transferred.			*
 *									*
 *   The information in this software is subject to change  without	*
 *   notice  and should not be construed as a commitment by Digital	*
 *   Equipment Corporation.						*
 *									*
 *   Digital assumes no responsibility for the use  or  reliability	*
 *   of its software on equipment which is not supplied by Digital.	*
 *									*
 ************************************************************************/
/*
 * Copyright 1985 by MIPS Computer Systems, Inc.
 */

/*
 * Modification History: cpu.h - cpu specific defines
 *
 * 09-Aug-90	Randall Brown
 *	Added SPLIO define.
 *
 * 29-Mar-90	gmm
 *	Changed spl6 and splhigh to be same as splclock (6)
 *
 * 30-Dec-89	bp
 *	Added field to cpu_archdep structure for determining whether a cpu
 *	is in an interrupt service routine.
 *
 * 28-Dec-89	Robin
 *	Added defines for R2000 cause register bits.
 *
 * 13-Oct-89    gmm
 *	SMP changes - added cpu_archdep and tlb_pid_state structures.
 *
 * 21-sep-89	burns
 *	ISIS pool merge for the following:
 *
 * 	13-May-89 -- kong
 *	changed NF_NENTRIES from 11 to 12, added new #define NF_INTR.
 *	See locore.s for details.
 *
 * 08-Jun-89 -- gmm
 *	Added define for IDLSTAK_OFF
 *
 * 02-May-89 -- jaw, jmartin
 *	fix forkutl to work on mips.
 *
 * 26-Apr-89 -- jmartin
 *	Add IS_Forkmap predicate.
 *
 * 07-Apr-89 -- afd
 *	Fixed CONS/PROM/MEM-PRINT flag values.
 *	Added IPLSIZE for the iplmask array (its the number of interrupt lines)
 *
 * 06-Feb-89 -- kong
 *	Added size of interrupt masks to include those for spl6, splhigh,
 *	spl7, and splextreme.
 *
 * 26-Jan-89 -- kong
 *	Added interrupt masks offsets.
 *
 * 06-Sep-88 -- afd
 *	Added SBE_ADDR, SEG_BITS, SPLblah defines.
 *
 */

#ifndef CPU_HDR
#define CPU_HDR

#ifdef KERNEL
#include "../h/ansi_compat.h"
#else
#include <ansi_compat.h>
#endif

/*
 * Segment base addresses and sizes
 */
#define	K0BASE		0x80000000
#define	K0SIZE		0x20000000
#define	K1BASE		0xA0000000
#define	K1SIZE		0x20000000
#define	K2BASE		0xC0000000
#define	K2SIZE		0x20000000
/*
 * KPTE window is 2 megabytes long and is placed
 * 4 Meg from the top of kseg2, to leave space for upage). 
 * KPTE windown must be on a 2 Meg boundary.
 * (Note: this definition relies upon 2's complement arithmetic!)
 */
#define	KPTEBASE	(-0x400000)
#define	KPTESIZE	0x200000
#define	KUBASE		0
#define	KUSIZE		0x80000000

/*
 * Exception vectors
 */
#define	UT_VEC		K0BASE			/* utlbmiss vector */
#define	E_VEC		(K0BASE+0x80)		/* exception vector */
#define	R_VEC		(K1BASE+0x1fc00000)	/* reset vector */

/*
 * Address conversion macros
 */
#define	K0_TO_K1(x)	((unsigned)(x)|0xA0000000)	/* kseg0 to kseg1 */
#define	K1_TO_K0(x)	((unsigned)(x)&0x9FFFFFFF)	/* kseg1 to kseg0 */
#define	K0_TO_PHYS(x)	((unsigned)(x)&0x1FFFFFFF)	/* kseg0 to physical */
#define	K1_TO_PHYS(x)	((unsigned)(x)&0x1FFFFFFF)	/* kseg1 to physical */
#define	PHYS_TO_K0(x)	((unsigned)(x)|0x80000000)	/* physical to kseg0 */
#define	PHYS_TO_K1(x)	((unsigned)(x)|0xA0000000)	/* physical to kseg1 */

/*
 * Address predicates
 */
#define	IS_KSEG0(x)	((unsigned)(x) >= K0BASE && (unsigned)(x) < K1BASE)
#define	IS_KSEG1(x)	((unsigned)(x) >= K1BASE && (unsigned)(x) < K2BASE)
#define	IS_KSEG2(x)	((unsigned)(x) >= K2BASE && (unsigned)(x) < KPTEBASE)
#define	IS_KPTESEG(x)	((unsigned)(x) >= KPTEBASE)
#define	IS_KUSEG(x)	((unsigned)(x) < K0BASE)
#define IS_Forkmap(x)	((unsigned)(x) >= (unsigned)Forkmap && \
			 (unsigned)(x) < (unsigned)(Forkmap + FORKPAGES))

/*
 * Cache size constants
 */
#define	MINCACHE	(4*1024)
#define	MAXCACHE	(64*1024)

/*
 * TLB size constants
 */
#define	TLBWIREDBASE	0		/* WAG for now */
#define	NWIREDENTRIES	8		/* WAG for now */
#define	TLBRANDOMBASE	NWIREDENTRIES
#define	NRANDOMENTRIES	(NTLBENTRIES-NWIREDENTRIES)
#define	NTLBENTRIES	64		/* WAG for now */

/*
 * tlb entrylo format
 */
#ifndef LOCORE
union tlb_lo {
	unsigned tl_word;		/* efficient access */
	struct {
#ifdef __MIPSEB
		unsigned tls_pfn:20;	/* physical page frame number */
		unsigned tls_n:1;	/* non-cacheable */
		unsigned tls_d:1;	/* dirty (actually writeable) */
		unsigned tls_v:1;	/* valid */
		unsigned tls_g:1;	/* match any pid */
		unsigned :8;
#endif /* __MIPSEB */
#ifdef __MIPSEL
		unsigned :8;
		unsigned tls_g:1;	/* match any pid */
		unsigned tls_v:1;	/* valid */
		unsigned tls_d:1;	/* dirty (actually writeable) */
		unsigned tls_n:1;	/* non-cacheable */
		unsigned tls_pfn:20;	/* physical page frame number */
#endif /* __MIPSEL */
	} tl_struct;
};

#define	tl_pfn		tl_struct.tls_pfn
#define	tl_n		tl_struct.tls_n
#define	tl_d		tl_struct.tls_d
#define	tl_v		tl_struct.tls_v
#define	tl_g		tl_struct.tls_g
#endif /* !LOCORE */

#define	TLBLO_PFNMASK	0xfffff000
#define	TLBLO_PFNSHIFT	12
#define	TLBLO_N		0x800		/* non-cacheable */
#define	TLBLO_D		0x400		/* writeable */
#define	TLBLO_V		0x200		/* valid bit */
#define	TLBLO_G		0x100		/* global access bit */

#define	TLBLO_FMT	"\20\14N\13D\12V\11G"

/*
 * TLB entryhi format
 */
#ifndef LOCORE
union tlb_hi {
	unsigned th_word;		/* efficient access */
	struct {
#ifdef __MIPSEB
		unsigned ths_vpn:20;	/* virtual page number */
		unsigned ths_pid:6;
		unsigned :6;
#endif /* __MIPSEB */
#ifdef __MIPSEL
		unsigned :6;
		unsigned ths_pid:6;
		unsigned ths_vpn:20;	/* virtual page number */
#endif /* __MIPSEL */
	} th_struct;
};

#define	th_vpn		th_struct.ths_vpn
#define	th_pid		th_struct.ths_pid
#endif /* !LOCORE */

#define	TLBHI_VPNMASK	0xfffff000
#define	TLBHI_VPNSHIFT	12
#define	TLBHI_PIDMASK	0xfc0
#define	TLBHI_PIDSHIFT	6
#define	TLBHI_NPID	64

/*
 * TLB index register
 */
#ifndef LOCORE
union tlb_inx {
	unsigned ti_word;
	struct {
#ifdef __MIPSEB
		unsigned tis_probe:1;	/* 1 => probe failure */
		unsigned :17;
		unsigned tis_inx:6;	/* tlb index for TLBWRITEI op */
		unsigned :8;
#endif /* __MIPSEB */
#ifdef __MIPSEL
		unsigned :8;
		unsigned tis_inx:6;	/* tlb index for TLBWRITEI op */
		unsigned :17;
		unsigned tis_probe:1;	/* 1 => probe failure */
#endif /* __MIPSEL */
	} ti_struct;
};

#define	ti_probe	ti_struct.tis_probe
#define	ti_inx		ti_struct.tis_inx
#endif /* !LOCORE */

#define	TLBINX_PROBE		0x80000000
#define	TLBINX_INXMASK		0x00003f00
#define	TLBINX_INXSHIFT		8

/*
 * TLB random register
 */
#ifndef LOCORE
union tlb_rand {
	unsigned tr_word;
	struct {
#ifdef __MIPSEB
		unsigned :18;
		unsigned trs_rand:6;	/* tlb index for TLBWRITER op */
		unsigned :8;
#endif /* __MIPSEB */
#ifdef __MIPSEL
		unsigned :8;
		unsigned trs_rand:6;	/* tlb index for TLBWRITER op */
		unsigned :18;
#endif /* __MIPSEL */
	} tr_struct;
};

#define	tr_rand		ti_struct.tis_rand
#endif /* !LOCORE */

#define	TLBRAND_RANDMASK	0x00003f00
#define	TLBRAND_RANDSHIFT	8

/*
 * TLB context register
 */
#ifndef LOCORE
union tlb_ctxt {
	unsigned tc_word;		/* efficient access */
	struct {
#ifdef __MIPSEB
		unsigned tcs_pteseg:11;	/* bits 21-31 of kernel pte window */
		unsigned tcs_vpn:19;	/* vpn of faulting ref (ro) */
		unsigned :2;
#endif /* __MIPSEB */
#ifdef __MIPSEL
		unsigned :2;
		unsigned tcs_vpn:19;	/* vpn of faulting ref (ro) */
		unsigned tcs_pteseg:11;	/* bits 22-31 of kernel pte window */
#endif /* __MIPSEL */
	} tc_struct;
};