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📁 <B>Digital的Unix操作系统VAX 4.2源码</B>
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#ifdef MIPS_ARCH_SPL_ORIG	lw	v0,mips_spl_arch_type	beq	v0,zero,splsoftclock_kn01#endif	.set	noreorder	li	v1, KN02BA_SPL_MASK	# disable interrupts	mtc0	v1, C0_SR	nop	lw	v0, ipllevel		# load return value with current ipl	li	v1, SPLSOFTC	sw	v1, ipllevel		# store new ipl into ipllevel	lw	a0, kn02ba_sim+SPLSOFTC*4 # get system interrupt mask value	lw	v1, splm+SPLSOFTC*4	# get status register mask value	sw	a0, KN02BA_SIRM_K1ADDR	# load mask register with value	lw	a0, KN02BA_SIRM_K1ADDR	# reread address to flush write buffer	mtc0	v1, C0_SR		# load status register with value	j	ra	nop	.set	reordersplsoftclock_kn01:#endif#ifdef MIPS_ARCH_SPL_ORIG	.set	noreorder	lw	v1,splm+SPLSOFTC*4	mfc0	v0,C0_SR	mtc0	v1,C0_SR	j	ra	nop	.set	reorder#endif	END(splsoftclock)/* * splnet: block against network software interrupts (level 2 softint). */LEAF(splnet)#ifdef DS5000_100#ifdef MIPS_ARCH_SPL_ORIG	lw	v0,mips_spl_arch_type	beq	v0,zero,splnet_kn01#endif	.set	noreorder	li	v1, KN02BA_SPL_MASK	# disable interrupts	mtc0	v1, C0_SR	nop	lw	v0, ipllevel		# load return value with current ipl	li	v1, SPLNET	sw	v1, ipllevel		# store new ipl into ipllevel	lw	a0, kn02ba_sim+SPLNET*4	# get system interrupt mask value	lw	v1, splm+SPLNET*4	# get status register mask value	sw	a0, KN02BA_SIRM_K1ADDR	# load mask register with value	lw	a0, KN02BA_SIRM_K1ADDR	# reread address to flush write buffer	mtc0	v1, C0_SR		# load status register with value	j	ra	nop	.set	reordersplnet_kn01:#endif#ifdef MIPS_ARCH_SPL_ORIG	.set	noreorder	lw	v1,splm+SPLNET*4	mfc0	v0,C0_SR	mtc0	v1,C0_SR	j	ra	nop	.set	reorder#endif	END(splnet)/* * splbio: block against all I/O device interrupts. all are vme */LEAF(splbio)#ifdef DS5000_100#ifdef MIPS_ARCH_SPL_ORIG	lw	v0,mips_spl_arch_type	beq	v0,zero,splbio_kn01#endif	.set	noreorder	li	v1, KN02BA_SPL_MASK	# disable interrupts	mtc0	v1, C0_SR	nop	lw	v0, ipllevel		# load return value with current ipl	li	v1, SPLIO	sw	v1, ipllevel		# store new ipl into ipllevel	lw	a0, kn02ba_sim+SPLIO*4	# get system interrupt mask value	lw	v1, splm+SPLIO*4	# get status register mask value	sw	a0, KN02BA_SIRM_K1ADDR	# load mask register with value	lw	a0, KN02BA_SIRM_K1ADDR	# reread address to flush write buffer	mtc0	v1, C0_SR		# load status register with value	j	ra	nop	.set	reordersplbio_kn01:#endif#ifdef MIPS_ARCH_SPL_ORIG	.set	noreorder	lw	v1,splm+SPLBIO*4	mfc0	v0,C0_SR	mtc0	v1,C0_SR	j	ra	nop	.set	reorder#endif	END(splbio)/* * splimp: block against network device interrupts * NOTE: the vax version of this routine blocks hardclocks. */LEAF(splimp)#ifdef DS5000_100#ifdef MIPS_ARCH_SPL_ORIG	lw	v0,mips_spl_arch_type	beq	v0,zero,splimp_kn01#endif	.set	noreorder	li	v1, KN02BA_SPL_MASK	# disable interrupts	mtc0	v1, C0_SR	nop	lw	v0, ipllevel		# load return value with current ipl	li	v1, SPLIO	sw	v1, ipllevel		# store new ipl into ipllevel	lw	a0, kn02ba_sim+SPLIO*4	# get system interrupt mask value	lw	v1, splm+SPLIO*4	# get status register mask value	sw	a0, KN02BA_SIRM_K1ADDR	# load mask register with value	lw	a0, KN02BA_SIRM_K1ADDR	# reread address to flush write buffer	mtc0	v1, C0_SR		# load status register with value	j	ra	nop	.set	reordersplimp_kn01:#endif#ifdef MIPS_ARCH_SPL_ORIG	.set	noreorder	lw	v1,splm+SPLIMP*4	mfc0	v0,C0_SR	mtc0	v1,C0_SR	j	ra	nop	.set	reorder#endif	END(splimp)/* * spltty: block against tty device interrupts. console uart and vme */LEAF(spltty)#ifdef DS5000_100#ifdef MIPS_ARCH_SPL_ORIG	lw	v0,mips_spl_arch_type	beq	v0,zero,spltty_kn01#endif	.set	noreorder	li	v1, KN02BA_SPL_MASK	# disable interrupts	mtc0	v1, C0_SR	nop	lw	v0, ipllevel		# load return value with current ipl	li	v1, SPLIO	sw	v1, ipllevel		# store new ipl into ipllevel	lw	a0, kn02ba_sim+SPLIO*4	# get system interrupt mask value	lw	v1, splm+SPLIO*4	# get status register mask value	sw	a0, KN02BA_SIRM_K1ADDR	# load mask register with value	lw	a0, KN02BA_SIRM_K1ADDR	# reread address to flush write buffer	mtc0	v1, C0_SR		# load status register with value	j	ra	nop	.set	reorderspltty_kn01:#endif#ifdef MIPS_ARCH_SPL_ORIG	.set	noreorder	lw	v1,splm+SPLTTY*4	mfc0	v0,C0_SR	mtc0	v1,C0_SR	j	ra	nop	.set	reorder#endif	END(spltty)/* * splcons: console output (same as tty for ULTRIX) */LEAF(splcons)#ifdef DS5000_100#ifdef MIPS_ARCH_SPL_ORIG	lw	v0,mips_spl_arch_type	beq	v0,zero,splcons_kn01#endif	.set	noreorder	li	v1, KN02BA_SPL_MASK	# disable interrupts	mtc0	v1, C0_SR	nop	lw	v0, ipllevel		# load return value with current ipl	li	v1, SPLIO	sw	v1, ipllevel		# store new ipl into ipllevel	lw	a0, kn02ba_sim+SPLIO*4	# get system interrupt mask value	lw	v1, splm+SPLIO*4	# get status register mask value	sw	a0, KN02BA_SIRM_K1ADDR	# load mask register with value	lw	a0, KN02BA_SIRM_K1ADDR	# reread address to flush write buffer	mtc0	v1, C0_SR		# load status register with value	j	ra	nop	.set	reordersplcons_kn01:#endif#ifdef MIPS_ARCH_SPL_ORIG	.set	noreorder	lw	v1,splm+SPLCONS*4	mfc0	v0,C0_SR	mtc0	v1,C0_SR	j	ra	nop	.set	reorder#endif	END(splcons)/* * splclock: block against sched clock interrupts. */LEAF(splclock)#ifdef DS5000_100#ifdef MIPS_ARCH_SPL_ORIG	lw	v0,mips_spl_arch_type	beq	v0,zero,splclock_kn01#endif	.set	noreorder	li	v1, KN02BA_SPL_MASK	# disable interrupts	mtc0	v1, C0_SR	nop	lw	v0, ipllevel		# load return value with current ipl	li	v1, SPLCLOCK	sw	v1, ipllevel		# store new ipl into ipllevel	lw	a0, kn02ba_sim+SPLCLOCK*4 # get system interrupt mask value	lw	v1, splm+SPLCLOCK*4	# get status register mask value	sw	a0, KN02BA_SIRM_K1ADDR	# load mask register with value	lw	a0, KN02BA_SIRM_K1ADDR	# reread address to flush write buffer	mtc0	v1, C0_SR		# load status register with value	j	ra	nop	.set	reordersplclock_kn01:#endif#ifdef MIPS_ARCH_SPL_ORIG	.set	noreorder	lw	v1,splm+SPLCLOCK*4	mfc0	v0,C0_SR	mtc0	v1,C0_SR	j	ra	nop	.set	reorder#endif	END(splclock)/* * splmem: block against memory error interrupts */LEAF(splmem)#ifdef DS5000_100#ifdef MIPS_ARCH_SPL_ORIG	lw	v0,mips_spl_arch_type	beq	v0,zero,splmem_kn01#endif	.set	noreorder	li	v1, KN02BA_SPL_MASK	# disable interrupts	mtc0	v1, C0_SR	nop	lw	v0, ipllevel		# load return value with current ipl	li	v1, SPLMEM	sw	v1, ipllevel		# store new ipl into ipllevel	lw	a0, kn02ba_sim+SPLMEM*4	# get system interrupt mask value	lw	v1, splm+SPLMEM*4	# get status register mask value	sw	a0, KN02BA_SIRM_K1ADDR	# load mask register with value	lw	a0, KN02BA_SIRM_K1ADDR	# reread address to flush write buffer	mtc0	v1, C0_SR		# load status register with value	j	ra	nop	.set	reordersplmem_kn01:#endif#ifdef MIPS_ARCH_SPL_ORIG	.set	noreorder	lw	v1,splm+SPLMEM*4	mfc0	v0,C0_SR	mtc0	v1,C0_SR	j	ra	nop	.set	reorder#endif	END(splmem)/* * splfpu: block against fpu interrupts */LEAF(splfpu)#ifdef DS5000_100#ifdef MIPS_ARCH_SPL_ORIG	lw	v0,mips_spl_arch_type	beq	v0,zero,splfpu_kn01#endif	.set	noreorder	li	v1, KN02BA_SPL_MASK	# disable interrupts	mtc0	v1, C0_SR	nop	lw	v0, ipllevel		# load return value with current ipl	li	v1, SPLEXTREME	sw	v1, ipllevel		# store new ipl into ipllevel	lw	a0, kn02ba_sim+SPLEXTREME*4# get system interrupt mask value	lw	v1, splm+SPLEXTREME*4	# get status register mask value	sw	a0, KN02BA_SIRM_K1ADDR	# load mask register with value	lw	a0, KN02BA_SIRM_K1ADDR	# reread address to flush write buffer	mtc0	v1, C0_SR		# load status register with value	j	ra	nop	.set	reordersplfpu_kn01:#endif#ifdef MIPS_ARCH_SPL_ORIG	.set	noreorder	lw	v1,splm+SPLFPU*4	mfc0	v0,C0_SR	mtc0	v1,C0_SR	j	ra	nop	.set	reorder#endif	END(splfpu)/* * splhigh: block against all device interrupts and clock interrupts. */LEAF(splhigh)#ifdef DS5000_100#ifdef MIPS_ARCH_SPL_ORIG	lw	v0,mips_spl_arch_type	beq	v0,zero,splhigh_kn01#endif	.set	noreorder	li	v1, KN02BA_SPL_MASK	# disable interrupts	mtc0	v1, C0_SR	nop	lw	v0, ipllevel		# load return value with current ipl	li	v1, SPLCLOCK	sw	v1, ipllevel		# store new ipl into ipllevel	lw	a0, kn02ba_sim+SPLCLOCK*4 # get system interrupt mask value	lw	v1, splm+SPLCLOCK*4	# get status register mask value	sw	a0, KN02BA_SIRM_K1ADDR	# load mask register with value	lw	a0, KN02BA_SIRM_K1ADDR	# reread address to flush write buffer	mtc0	v1, C0_SR		# load status register with value	j	ra	nop	.set	reordersplhigh_kn01:#endif#ifdef MIPS_ARCH_SPL_ORIG	.set	noreorder	lw	v1,splm+SPLHIGH*4	mfc0	v0,C0_SR	mtc0	v1,C0_SR	j	ra	nop	.set	reorder#endif	END(splhigh)/* * spl6: block against all device interrupts and clock interrupts. */LEAF(spl6)#ifdef DS5000_100#ifdef MIPS_ARCH_SPL_ORIG	lw	v0,mips_spl_arch_type	beq	v0,zero,spl6_kn01#endif	.set	noreorder	li	v1, KN02BA_SPL_MASK	# disable interrupts	mtc0	v1, C0_SR	nop	lw	v0, ipllevel		# load return value with current ipl	li	v1, SPLCLOCK	sw	v1, ipllevel		# store new ipl into ipllevel	lw	a0, kn02ba_sim+SPLCLOCK*4 # get system interrupt mask value	lw	v1, splm+SPLCLOCK*4	# get status register mask value	sw	a0, KN02BA_SIRM_K1ADDR	# load mask register with value	lw	a0, KN02BA_SIRM_K1ADDR	# reread address to flush write buffer	mtc0	v1, C0_SR		# load status register with value	j	ra	nop	.set	reorderspl6_kn01:#endif#ifdef MIPS_ARCH_SPL_ORIG	.set	noreorder	lw	v1,splm+SPL6*4	mfc0	v0,C0_SR	mtc0	v1,C0_SR	j	ra	nop	.set	reorder#endif	END(spl6)/* * spl7: block against all interrupts except HALT interrupts, which is * never blocked. */LEAF(spl7)#ifdef DS5000_100#ifdef MIPS_ARCH_SPL_ORIG	lw	v0,mips_spl_arch_type	beq	v0,zero,spl7_kn01#endif	.set	noreorder	li	v1, KN02BA_SPL_MASK	# disable interrupts	mtc0	v1, C0_SR	nop	lw	v0, ipllevel		# load return value with current ipl	li	v1, SPLEXTREME	sw	v1, ipllevel		# store new ipl into ipllevel	lw	a0, kn02ba_sim+SPLEXTREME*4# get system interrupt mask value	lw	v1, splm+SPLEXTREME*4	# get status register mask value	sw	a0, KN02BA_SIRM_K1ADDR	# load mask register with value	lw	a0, KN02BA_SIRM_K1ADDR	# reread address to flush write buffer	mtc0	v1, C0_SR		# load status register with value	j	ra	nop	.set	reorderspl7_kn01:#endif#ifdef MIPS_ARCH_SPL_ORIG	.set	noreorder	lw	v1,splm+SPL7*4	mfc0	v0,C0_SR	mtc0	v1,C0_SR	j	ra	nop	.set	reorder#endif	END(spl7)/* * splextreme: block against all interrupts except HALT interrupts, which is * never blocked. */LEAF(splextreme)#ifdef DS5000_100#ifdef MIPS_ARCH_SPL_ORIG	lw	v0,mips_spl_arch_type	beq	v0,zero,splextreme_kn01#endif	.set	noreorder	li	v1, KN02BA_SPL_MASK	# disable interrupts	mtc0	v1, C0_SR	nop	lw	v0, ipllevel		# load return value with current ipl	li	v1, SPLEXTREME	sw	v1, ipllevel		# store new ipl into ipllevel	lw	a0, kn02ba_sim+SPLEXTREME*4# get system interrupt mask value	lw	v1, splm+SPLEXTREME*4	# get status register mask value	sw	a0, KN02BA_SIRM_K1ADDR	# load mask register with value	lw	a0, KN02BA_SIRM_K1ADDR	# reread address to flush write buffer	mtc0	v1, C0_SR		# load status register with value	j	ra	nop	.set	reordersplextreme_kn01:#endif#ifdef MIPS_ARCH_SPL_ORIG	.set	noreorder	lw	v1,splm+SPLEXTREME*4	mfc0	v0,C0_SR	mtc0	v1,C0_SR	j	ra	nop	.set	reorder#endif	END(splextreme)/* * splx(ipl) -- restore previously saved ipl */LEAF(splx)#ifdef DS5000_100#ifdef MIPS_ARCH_SPL_ORIG	lw	v0,mips_spl_arch_type	beq	v0,zero,splx_kn01#endif	.set	noreorder	li	v1, KN02BA_SPL_MASK	mtc0	v1, C0_SR		# disable interrupts	nop	lw	v0, ipllevel		# load return value with current ipl	sll	a1, a0, 2		# multiply by 4	lw	v1, kn02ba_sim(a1)	# get system interrupt mask value	sw	a0, ipllevel		# store new ipl into ipllevel	lw	a2, splm(a1)		# get status register mask value	sw	v1, KN02BA_SIRM_K1ADDR	# load mask register with value	lw	v1, KN02BA_SIRM_K1ADDR	# reread address to flush write buffer	mtc0	a2, C0_SR		# load status register with new mask	j	ra	nop	.set	reordersplx_kn01:#endif#ifdef MIPS_ARCH_SPL_ORIG	.set	noreorder	mfc0	v0,C0_SR/* Temporary fix to avoid caller setting BEV bit in status register */	li	t0,0xffbfffff	# Get the BEV bit	and	a0,t0		# Clear BEV bit	nop	mtc0	a0,C0_SR	j	ra	nop	.set	reorder#endif	END(splx)/* * get_cause: get current value of cause register */LEAF(get_cause)	.set noreorder	nop	mfc0	v0,C0_CAUSE	nop	.set reorder	j	ra	END(get_cause)/* * get_status_reg: get current value of cause register */LEAF(get_status_reg)	.set noreorder	nop	mfc0	v0,C0_SR	nop	.set reorder	j	ra	END(get_status_reg)LEAF(kn01_getspl)	.set noreorder	nop	mfc0	v0,C0_SR	nop	.set reorder	j	ra	END(kn01_getspl)/* * clear_bev -- Change the control of TLB and general exception vectors to be * handled by the kernel and not the console.  This needs to be done after * the exception handling bcopy of the vector code in the processor specific. */LEAF(clear_bev)	.set noreorder	mfc0	v0,C0_SR		# get contents of SR	li	t0,(~SR_BEV)		# set up not of BEV bit	nop	and	v0,t0			# clear the BEV bit	nop	mtc0	v0,C0_SR	j	ra	nop
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