ciport.h

<B>Digital的Unix操作系统VAX 4.2源码</B>

#define	CIXCD_PDCSR	    0x0020	/* Port diag. control & status reg */
#define	CIXCD_PSR	    0x0024	/* Port status register */
#define	CIXCD_XFAER	    0x002C	/* XMI failing address lw1 reg*/

#define	CIXCD_PQBBASE	    0x1000	/* PQB base register 		     */
#define	CIXCD_PESR	    0x1008	/* Port error status register	     */
#define	CIXCD_PFAR	    0x100C	/* Port failing address register     */
#define	CIXCD_PPR	    0x1010	/* Port parameter register	     */
#define	CIXCD_PSNR	    0x1014	/* Port serial number reg */
#define	CIXCD_PIDR	    0x1018	/* Port interrupt destination reg    */
#define	CIXCD_PVR	    0x1020	/* Port vector register		     */
#define	CIXCD_PCQ0CR	    0x1028	/* Port command queue 0 control reg  */
#define	CIXCD_PCQ1CR	    0x102C	/* Port command queue 1 control reg  */
#define	CIXCD_PCQ2CR	    0x1030	/* Port command queue 2 control reg  */
#define	CIXCD_PCQ3CR	    0x1034	/* Port command queue 3 control reg  */
#define	CIXCD_PSRCR	    0x1038	/* Port status release control reg   */
#define	CIXCD_PECR	    0x103C	/* Port enable control register      */
#define	CIXCD_PDCR	    0x1040	/* Port disable control register     */
#define	CIXCD_PICR	    0x1044	/* Port initialization control reg   */
#define	CIXCD_PDFQCR	    0x1048	/* Port dg free queue control reg    */
#define	CIXCD_PMFQCR	    0x104C	/* Port msg free queue control reg   */
#define	CIXCD_PMTCR	    0x1050	/* Port maintenance timer control reg*/
#define	CIXCD_PMTECR	    0x1054	/* Port maint timer expiration ctl reg*/
#define	CIXCD_PPER	    0x1058	/* Port parameter ext. register	     */
#define	CIXCD_PPE2R	    0x101C	/* Port parameter ext. 2 register    */

					/* CIDASH Register Offsets 	     */
#define	CIKMF_XFAER	    0x000C	/* XMI failing address lw1 reg PASS1 */
/*#define	CIKMF_XCOMM	    0x0010*//* XMI COMM address  reg PASS2 */
#define	CIKMF_XPCSER1	    0x0010	/* register PASS1     */
#define	CIKMF_XPCSER2	    0x0014	/* register PASS1     */
#define	CIKMF_XPCCTRL	    0x0018	/* reg */
#define	CIKMF_XPCSTAT1	    0x001C	/* reg*/
#define	CIKMF_XPCSTAT2	    0x0020	/* reg */
#define	CIKMF_XBIST	    0x0024	/* register */
#define	CIKMF_XPCCSR	    0x0028	/* register */
/*#define	CIKMF_XPCPSER1	    0x0020*//* register	PASS2 */
/*#define	CIKMF_XPCPSER2	    0x0024*//* register PASS2 */
/*#define	CIKMF_XFAER	    0x002C*//* XMI failing address lw1 reg PASS2 */
#define	CIKMF_IPL1	    0x0030	/* register */
#define	CIKMF_IPL2	    0x0034	/* register */
#define	CIKMF_IPL3	    0x0038	/* register */
#define	CIKMF_IDEST1	    0x003C	/* register */
#define	CIKMF_IDEST2	    0x0040	/* register */
#define	CIKMF_IDEST3	    0x0044	/* register */
#define	CIKMF_IVECT1	    0x0048	/* register */
#define	CIKMF_IVECT2	    0x004C	/* register */
#define	CIKMF_IVECT3	    0x0050	/* register */

					/* DASHAC1 Specific Registers 	*/
#define CIKMF_SSWCR1	    0x4030	/* Shac software chip reset	*/
#define CIKMF_SSHMA1	    0x4044	/* Shac shared host mem addr	*/
#define CIKMF_SLAVE_ADD1    0x4070	/*				*/
#define CIKMF_DRI1	    0x4074	/*				*/
#define CIKMF_DRO1	    0x4078	/*				*/

					/* DASHAC1 CI Port Registers 	*/
#define CIKMF_PQBBR1	    0x4048	/* PQB base register		*/
#define CIKMF_PSR1	    0x404C	/* Port status register		*/
#define CIKMF_PESR1	    0x4050	/* Port error status register	*/
#define CIKMF_PFAR1	    0x4054	/* Port failing address register*/
#define CIKMF_PPR1	    0x4058	/* Port parameter register	*/
#define CIKMF_PMCSR1	    0x405C	/* Port maintenance cntl & status reg*/
#define CIKMF_PCQ0CR1	    0x4080	/* Port command queue 0 control reg*/
#define CIKMF_PCQ1CR1	    0x4084	/* Port command queue 1 control reg*/
#define CIKMF_PCQ2CR1	    0x4088	/* Port command queue 2 control reg*/
#define CIKMF_PCQ3CR1	    0x408C	/* Port command queue 3 control reg*/
#define CIKMF_PDFQCR1	    0x4090	/* Port dg free queue control reg*/
#define CIKMF_PMFQCR1	    0x4094	/* Port msg free queue control reg*/
#define CIKMF_PSRCR1	    0x4098	/* Port status release control reg*/
#define CIKMF_PECR1	    0x409C	/* Port enable control register	*/
#define CIKMF_PDCR1	    0x40A0	/* Port disable control register*/
#define CIKMF_PICR1	    0x40A4	/* Port initialization control reg */
#define CIKMF_PMTCR1	    0x40A8	/* Port maint timer control reg */
#define CIKMF_PMTEC1	    0x40AC	/* Port maint timer expiration ctl reg*/

					/* DASHAC2 Specific Registers 	*/
#define CIKMF_SSWCR2	    0x4230	/* Shac software chip reset	*/
#define CIKMF_SSHMA2	    0x4244	/* Shac shared host mem addr	*/
#define CIKMF_SLAVE_ADD2    0x4270	/*				*/
#define CIKMF_DRI2	    0x4274	/*				*/
#define CIKMF_DRO2	    0x4278	/*				*/

					/* DASHAC2 CI Port Registers 	*/
#define CIKMF_PQBBR2	    0x4248	/* PQB base register		*/
#define CIKMF_PSR2	    0x424C	/* Port status register		*/
#define CIKMF_PESR2	    0x4250	/* Port error status register	*/
#define CIKMF_PFAR2	    0x4254	/* Port failing address register*/
#define CIKMF_PPR2	    0x4258	/* Port parameter register	*/
#define CIKMF_PMCSR2	    0x425C	/* Port maintenance cntl & status reg*/
#define CIKMF_PCQ0CR2	    0x4280	/* Port command queue 0 control reg*/
#define CIKMF_PCQ1CR2	    0x4284	/* Port command queue 1 control reg*/
#define CIKMF_PCQ2CR2	    0x4288	/* Port command queue 2 control reg*/
#define CIKMF_PCQ3CR2	    0x428C	/* Port command queue 3 control reg*/
#define CIKMF_PDFQCR2	    0x4290	/* Port dg free queue control reg*/
#define CIKMF_PMFQCR2	    0x4294	/* Port msg free queue control reg*/
#define CIKMF_PSRCR2	    0x4298	/* Port status release control reg*/
#define CIKMF_PECR2	    0x429C	/* Port enable control register	*/
#define CIKMF_PDCR2	    0x42A0	/* Port disable control register*/
#define CIKMF_PICR2	    0x42A4	/* Port initialization control reg */
#define CIKMF_PMTCR2	    0x42A8	/* Port maint timer control reg */
#define CIKMF_PMTEC2	    0x42AC	/* Port maint timer expiration ctl reg*/

					/* SHAC CI Port Registers 	*/
#define CISHC_SSWCR	    0x0030	/* Shac software chip reset	*/
#define CISHC_SSHMA	    0x0044	/* Shac shared host mem addr	*/
#define CISHC_PQBBR	    0x0048	/* PQB base register		*/
#define CISHC_PSR	    0x004C	/* Port status register		*/
#define CISHC_PESR	    0x0050	/* Port error status register	*/
#define CISHC_PFAR	    0x0054	/* Port failing address register*/
#define CISHC_PPR	    0x0058	/* Port parameter register	*/
#define CISHC_PMCSR	    0x005C	/* Port maintenance cntl & status reg*/
#define CISHC_PCQ0CR	    0x0080	/* Port command queue 0 control reg*/
#define CISHC_PCQ1CR	    0x0084	/* Port command queue 1 control reg*/
#define CISHC_PCQ2CR	    0x0088	/* Port command queue 2 control reg*/
#define CISHC_PCQ3CR	    0x008C	/* Port command queue 3 control reg*/
#define CISHC_PDFQCR	    0x0090	/* Port dg free queue control reg*/
#define CISHC_PMFQCR	    0x0094	/* Port msg free queue control reg*/
#define CISHC_PSRCR	    0x0098	/* Port status release control reg*/
#define CISHC_PECR	    0x009C	/* Port enable control register	*/
#define CISHC_PDCR	    0x00A0	/* Port disable control register*/
#define CISHC_PICR	    0x00A4	/* Port initialization control reg */
#define CISHC_PMTCR	    0x00A8	/* Port maint timer control reg */
#define CISHC_PMTEC	    0x00AC	/* Port maint timer expiration ctl reg*/

					/* Miscellaneous Constants	     */
#define	MAX_CABLES		 2	/* Maximum cable number		     */

/* CI Register Definitions.
 */
					/* BIIC Error Register Bit Masks     */
#define	CIBCA_MSE_ERRS	0x297F0000	/* CIBCA memory system errs BER mask */
#define	CIBCI_MSE_ERRS	0x013F0000	/* CIBCI memory system errs BER mask */
#define	CIBCI_PAR_ERRS  0x08C00000	/* CIBCI parity errors BER mask	     */

					/* CIBCA/CIXCD BIIC/XMI Device Type  */
					/*  Register Port/Hardware Revision  */
					/*  Field Mask Bits		     */
#define	CIBX_DEV_UCODE	  0x800000	/* Port microcode is onboard	     */

					/* CI750/CI780 Configuration Register*/
					/*   Mask Bits			     */
#define	CI780_CNF_ADAP	0x000000FF	/* Adapter code( device type )	     */
#define	CI780_CNF_PFD	0x00000100	/* Power fail disable		     */
#define	CI780_CNF_TDEAD	0x00000200	/* Transmit dead( CI780 )	     */
#define	CI780_CNF_TDCLO	0x00000200	/* Transmit DCLO( CI750 ) 	     */
#define	CI780_CNF_TFAIL	0x00000400	/* Transmit fail( CI780 )	     */
#define	CI780_CNF_TACLO	0x00000400	/* Transmit ACLO( CI750 ) 	     */
#define	CI780_CNF_NOCI	0x00001000	/* Adapter not present( CI750 )      */
#define	CI780_CNF_CTO	0x00002000	/* CI port timeout( CI750 )	     */
#define	CI780_CNF_CBPE	0x00008000	/* CI port parity error( CI750 )     */
#define	CI780_CNF_CRD	0x00010000	/* Corrected read data		     */
#define	CI780_CNF_UCE	0x00020000	/* Uncorrectable data error( CI750 ) */
#define	CI780_CNF_RDS	0x00020000	/* Read data substitute( CI780 )     */
#define	CI780_CNF_CXTER	0x00040000	/* Command transmit error( CI780 )   */
#define	CI780_CNF_RLTO	0x00080000	/* Readlock transfer timeout( CI750 )*/
#define	CI780_CNF_RDTO	0x00080000	/* Read data timeout( CI780 )	     */
#define	CI780_CNF_NXM	0x00100000	/* Nonexistent memory( CI750 )	     */
#define	CI780_CNF_CXTMO	0x00100000	/* Command transmit timeout( CI780 ) */
#define	CI780_CNF_PUP	0x00400000	/* Power up			     */
#define	CI780_CNF_PDWN	0x00800000	/* Power down			     */
#define	CI780_CNF_XMT	0x04000000	/* Transmit fault( CI780 )	     */
#define	CI780_CNF_MXT	0x08000000	/* Multiple transmit fault( CI780 )  */
#define	CI780_CNF_ISEQ	0x10000000	/* Interlocked seq fault( CI780 )    */
#define	CI780_CNF_URD	0x20000000	/* Unexpected read fault( CI780 )    */
#define	CI780_CNF_WSQ	0x40000000	/* Write sequence fault( CI780 )     */
#define	CI780_CNF_PAR	0x80000000	/* Parity fault( CI780 )	     */
#define	CI780_CNF_SBI	0xFC000000	/* SBI fault CNFR mask( CI780 )      */
#define	CI780_CNF_MSE	0x001E0000	/* Memory system error CNFR mask     */
#define	CI780_CNF_ERRS	0x03FEFF00	/* Configuration register error bits */

					/* CIBCI Configuration Register Mask */
					/*  Bits			     */
#define	CIBCI_CNF_NOCI	0x00800000	/* Port not present		     */
#define	CIBCI_CNF_DCLO	0x01000000	/* Port without power or uncabled    */
#define	CIBCI_CNF_PUP	0x04000000	/* Power up			     */
#define	CIBCI_CNF_PDWN	0x08000000	/* Power down			     */
#define	CIBCI_CNF_BBE	0x10000000	/* BI busy error		     */
#define	CIBCI_CNF_BIPE	0x20000000	/* BI parity error		     */
#define	CIBCI_CNF_BAPE	0x40000000	/* BI adapter parity error	     */
#define	CIBCI_CNF_CPPE	0x80000000	/* Internal bus parity error	     */
#define	CIBCI_CNF_ERRS	0xff800000	/* Configuration register error bits */
#define	CIBCI_CNF_PE	0xe0000000	/* Configuration register parity errs*/

					/* Port Control Register Mask Bits   */
#define	PCQ0CR_CMDQ0C	0x00000001	/* Port Command queue 0 control      */
#define	PCQ1CR_CMDQ1C	0x00000001	/* Port Command queue 1 control      */
#define	PCQ2CR_CMDQ2C	0x00000001	/* Port Command queue 2 control      */
#define	PCQ3CR_CMDQ3C	0x00000001	/* Port Command queue 3 control      */
#define	PDFQCR_DFQC	0x00000001	/* Port Datagram free queue control  */
#define	PMFQCR_MFQC	0x00000001	/* Port Message free queue control   */
#define	PDCR_PDC	0x00000001	/* Port disable control		     */
#define	PICR_PIC	0x00000001	/* Port initialize control	     */
#define	PECR_PEC	0x00000001	/* Port enable control		     */
#define	PMTCR_MTC	0x00000001	/* Port Maintenance timer control    */
#define	PSRCR_PSRC	0x00000001	/* Port status reg release control   */

					/* Port Error Status Register	     */
					/*   Miscellaneous Error Codes	     */
#define	PESR_BRKLINK		14	/* Broken link module( L0100 )	     */
					/*  ( CI750/CI780/CIBCI only )

					/* CI750/CI780/CIBCI Port Maintenance*/
					/*  Control and Status Register Mask */
					/*  Bits			     */
#define	CI7B_PMCS_MIN	0x00000001	/* Maintenance initialize	     */
#define	CI7B_PMCS_MIE	0x00000004	/* Maintenance interrupt enable	     */
#define	CI7B_PMCS_MIF	0x00000008	/* Maintenance interrupt flag	     */
#define	CI7B_PMCS_PSA	0x00000040	/* Programmable starting address     */
#define	CI7B_PMCS_XBPE	0x00000100	/* Transmit buffer parity error	     */
#define	CI7B_PMCS_OPE	0x00000200	/* Output parity error		     */
#define	CI7B_PMCS_IPE	0x00000400	/* Input parity error( CI780 )	     */
#define	CI7B_PMCS_CBPE	0x00000400	/* Adapter bus error( CI750/CIBCI )  */
#define	CI7B_PMCS_XMPE	0x00000800	/* Transmit buffer parity error	     */
#define	CI7B_PMCS_RBPE	0x00001000	/* Receive buffer parity error	     */
#define	CI7B_PMCS_LSPE	0x00002000	/* Local store parity error	     */
#define	CI7B_PMCS_CSPE	0x00004000	/* Control store parity error	     */
#define	CI7B_PMCS_PE	0x00008000	/* Parity error			     */

					/* CIBCA Port Maintenance Control and*/
					/*  Status Register Mask Bits	     */
#define	CIBX_PMCS_START	0x00000001	/* Start sequencer( CIBCA )	     */
#define	CIBX_PMCS_MIE	0x00000020	/* Maintenance interrupt enable	     */
#define	CIBX_PMCS_HALT	0x00000080	/* Halt sequencer		     */
#define	CIBCA_PMCS_BTO	0x00000100	/* BI bus timeout		     */
#define	CIBCA_PMCS_IIPE	0x00000200	/* II parity error		     */
#define	CIBCA_PMCS_MBIE	0x00000400	/* MAP BCI/BI error		     */
#define	CIBX_PMCS_CPE	0x00000800	/* CILP parity error		     */
#define	CIBX_PMCS_XMPE	0x00001000	/* Transmit buffer parity error	     */
#define	CIBX_PMCS_IBPE	0x00002000	/* Internal bus parity error	     */
#define	CIBX_PMCS_CSPE	0x00004000	/* Control store parity error	     */
#define	CIBCA_PMCS_BCIP	0x00008000	/* BCI parity error		     */

					/* CIXCD Port Maintenance Control */
#define	CIXCD_PMCS_MIN	0x00000001	/* Maintence initialize		     */
#define	CIXCD_PMCS_MIE	0x00000004	/* Maintence interrupt enable	     */
#define	CIXCD_PMCS_CPDE	0X00000010	/* CPU no responce error	     */
#define	CIXCD_PMCS_CPER	0X00000020	/* CPU error status	  	    */
#define	CIXCD_PMCS_PRER	0X00000040	/* Port read error responce	     */
#define	CIXCD_PMCS_PWER	0X00000080	/* Port write error responce	     */
#define	CIXCD_PMCS_STUF	0X00000100	/* ustack underflow error	     */
#define	CIXCD_PMCS_STOF	0x00000200	/* ustack overflow error	     */
#define	CIXCD_PMCS_YRPE	0X00000400	/* Y register parity error	     */
#define	CIXCD_PMCS_XRPE	0X00000800	/* X register parity error	     */
#define	CIXCD_PMCS_IBPE	0X00001000	/*  error	     */
#define	CIXCD_PMCS_CSPE	0X00002000	/*  error	     */