civar.c

<B>Digital的Unix操作系统VAX 4.2源码</B>

					/* Mandatory PD Functions for CI PPD */
		    ci_get_port,	/* Retrieve Port Number from Buffer  */
     ( u_long (*)())ci_init_port,	/* Initialize/Re-initialize a Port   */
     ( u_long (*)())ci_log_badport,	/* Log CI Originating Bad Port Number*/
		    ci_send_reqid,	/* Request Remote Port Identification*/
		    ci_set_circuit,	/* Set Virtual Circuit State - On/Off*/

					/* Optional PD Functions for CI PPD  */
		    ci_alloc_buf,	/* Allocate Emergency Command Packets*/
     ( u_long (*)())ci_dealloc_buf,	/* Deallocate Emergency Command Pkts */
     ( u_long (*)())ci_init_pb,		/* Initialize a Path Block	     */
     ( u_long (*)())ci_inv_cache,	/* Invalidate Port Translation Cache */
     ( u_long (*)())ci_notify_port,	/* Notify Port of CI PPD Activity    */
     ( u_long (*)())ci_test_lpconn,	/* Test Local Port Connectivity	     */
     ( u_long (*)())ci_update_ptype	/* Update Hardware Port Type	     */
};
u_long	*ci780_regoff[] = 	{	/* CI780/CI750 Register Offsets	     */
	    ( u_long * )CI780_CNFR,	/* Configuration register	     */
	    ( u_long * )CI780_MADR,	/* Maintenance address register      */
	    ( u_long * )CI780_MDATR,	/* Maintenance data register	     */
	    ( u_long * )CI780_PMCSR,	/* Port maintenance cntl & status reg*/
	    ( u_long * )CI7B_PSR,	/* Port status register		     */
	    ( u_long * )CI7B_PQBBASE,	/* PQB base register 		     */
	    ( u_long * )CI7B_PCQ0CR,	/* Port command queue 0 control reg  */
	    ( u_long * )CI7B_PCQ1CR,	/* Port command queue 1 control reg  */
	    ( u_long * )CI7B_PCQ2CR,	/* Port command queue 2 control reg  */
	    ( u_long * )CI7B_PCQ3CR,	/* Port command queue 3 control reg  */
	    ( u_long * )CI7B_PSRCR,	/* Port status release control reg   */
	    ( u_long * )CI7B_PECR,	/* Port enable control register      */
	    ( u_long * )CI7B_PDCR,	/* Port disable control register     */
	    ( u_long * )CI7B_PICR,	/* Port initialization control reg   */
	    ( u_long * )CI7B_PDFQCR,	/* Port dg free queue control reg    */
	    ( u_long * )CI7B_PMFQCR,	/* Port msg free queue control reg   */
	    ( u_long * )CI7B_PMTCR,	/* Port maintenance timer control reg*/
	    ( u_long * )CI7B_PFAR,	/* Port failing address register     */
	    ( u_long * )CI7B_PESR,	/* Port error status register	     */
	    ( u_long * )CI7B_PPR,	/* Port parameter register	     */
	    ( u_long * )0	 	/* Port parameter ext. register	     */
};
u_long	*cibci_regoff[] = {		/* CIBCI Register Offsets	     */
	    ( u_long * )CIBCI_CNFR,	/* Configuration register	     */
	    ( u_long * )CIBCI_MADR,	/* Maintenance address register      */
	    ( u_long * )CIBCI_MDATR,	/* Maintenance data register	     */
	    ( u_long * )CIBCI_PMCSR,	/* Port maintenance cntl & status reg*/
	    ( u_long * )CI7B_PSR,	/* Port status register		     */
	    ( u_long * )CI7B_PQBBASE,	/* PQB base register 		     */
	    ( u_long * )CI7B_PCQ0CR,	/* Port command queue 0 control reg  */
	    ( u_long * )CI7B_PCQ1CR,	/* Port command queue 1 control reg  */
	    ( u_long * )CI7B_PCQ2CR,	/* Port command queue 2 control reg  */
	    ( u_long * )CI7B_PCQ3CR,	/* Port command queue 3 control reg  */
	    ( u_long * )CI7B_PSRCR,	/* Port status release control reg   */
	    ( u_long * )CI7B_PECR,	/* Port enable control register      */
	    ( u_long * )CI7B_PDCR,	/* Port disable control register     */
	    ( u_long * )CI7B_PICR,	/* Port initialization control reg   */
	    ( u_long * )CI7B_PDFQCR,	/* Port dg free queue control reg    */
	    ( u_long * )CI7B_PMFQCR,	/* Port msg free queue control reg   */
	    ( u_long * )CI7B_PMTCR,	/* Port maintenance timer control reg*/
	    ( u_long * )CI7B_PFAR,	/* Port failing address register     */
	    ( u_long * )CI7B_PESR,	/* Port error status register	     */
	    ( u_long * )CI7B_PPR,	/* Port parameter register	     */
	    ( u_long * )0	 	/* Port parameter ext. register	     */
};
u_long	*cibca_regoff[] = {		/* CIBCA Register Offsets	     */
	    ( u_long * )0,		/* Configuration register	     */
	    ( u_long * )CIBCA_MADR,	/* Maintenance address register      */
	    ( u_long * )CIBCA_MDATR,	/* Maintenance data register	     */
	    ( u_long * )CIBX_PMCSR,	/* Port maintenance cntl & status reg*/
	    ( u_long * )CIBX_PSR,	/* Port status register		     */
	    ( u_long * )CIBCA_PQBBASE,	/* PQB base register 		     */
	    ( u_long * )CIBX_PCQ0CR,	/* Port command queue 0 control reg  */
	    ( u_long * )CIBX_PCQ1CR,	/* Port command queue 1 control reg  */
	    ( u_long * )CIBX_PCQ2CR,	/* Port command queue 2 control reg  */
	    ( u_long * )CIBX_PCQ3CR,	/* Port command queue 3 control reg  */
	    ( u_long * )CIBX_PSRCR,	/* Port status release control reg   */
	    ( u_long * )CIBX_PECR,	/* Port enable control register      */
	    ( u_long * )CIBX_PDCR,	/* Port disable control register     */
	    ( u_long * )CIBX_PICR,	/* Port initialization control reg   */
	    ( u_long * )CIBX_PDFQCR,	/* Port dg free queue control reg    */
	    ( u_long * )CIBX_PMFQCR,	/* Port msg free queue control reg   */
	    ( u_long * )CIBX_PMTCR,	/* Port maintenance timer control reg*/
	    ( u_long * )CIBCA_PFAR,	/* Port failing address register     */
	    ( u_long * )CIBCA_PESR,	/* Port error status register	     */
	    ( u_long * )CIBCA_PPR,	/* Port parameter register	     */
	    ( u_long * )0	 	/* Port parameter ext. register	     */
};
u_long	*cixcd_regoff[] = {		/* CIXCD Register Offsets	     */
	    ( u_long * )0,		/* Configuration register	     */
	    ( u_long * )0,		/* Maintenance address register      */
	    ( u_long * )0,		/* Maintenance data register	     */
	    ( u_long * )CIXCD_PMCSR,	/* Port maintenance cntl & status reg*/
	    ( u_long * )CIXCD_PSR,	/* Port status register		     */
	    ( u_long * )CIXCD_PQBBASE,	/* PQB base register 		     */
	    ( u_long * )CIXCD_PCQ0CR,	/* Port command queue 0 control reg  */
	    ( u_long * )CIXCD_PCQ1CR,	/* Port command queue 1 control reg  */
	    ( u_long * )CIXCD_PCQ2CR,	/* Port command queue 2 control reg  */
	    ( u_long * )CIXCD_PCQ3CR,	/* Port command queue 3 control reg  */
	    ( u_long * )CIXCD_PSRCR,	/* Port status release control reg   */
	    ( u_long * )CIXCD_PECR,	/* Port enable control register      */
	    ( u_long * )CIXCD_PDCR,	/* Port disable control register     */
	    ( u_long * )CIXCD_PICR,	/* Port initialization control reg   */
	    ( u_long * )CIXCD_PDFQCR,	/* Port dg free queue control reg    */
	    ( u_long * )CIXCD_PMFQCR,	/* Port msg free queue control reg   */
	    ( u_long * )CIXCD_PMTCR,	/* Port maintenance timer control reg*/
	    ( u_long * )CIXCD_PFAR,	/* Port failing address register     */
	    ( u_long * )CIXCD_PESR,	/* Port error status register	     */
	    ( u_long * )CIXCD_PPR,	/* Port parameter register	     */
	    ( u_long * )CIXCD_PPER	/* Port parameter ext. register	     */
};
u_long	*cikmf1_regoff[] = {		/* CIKMF CI Port 1 Register Offsets  */
	    ( u_long * )0,		/* Configuration register	     */
	    ( u_long * )CIKMF_XPCSER1, 	/* XPC port specific error register*/
	    ( u_long * )CIKMF_XPCSTAT1,	/* XPC port status register	     */
	    ( u_long * )CIKMF_PMCSR1,	/* Port maintenance cntl & status reg*/
	    ( u_long * )CIKMF_PSR1,	/* Port status register		     */
	    ( u_long * )CIKMF_PQBBR1,	/* PQB base register 		     */
	    ( u_long * )CIKMF_PCQ0CR1,	/* Port command queue 0 control reg  */
	    ( u_long * )CIKMF_PCQ1CR1,	/* Port command queue 1 control reg  */
	    ( u_long * )CIKMF_PCQ2CR1,	/* Port command queue 2 control reg  */
	    ( u_long * )CIKMF_PCQ3CR1,	/* Port command queue 3 control reg  */
	    ( u_long * )CIKMF_PSRCR1,	/* Port status release control reg   */
	    ( u_long * )CIKMF_PECR1,	/* Port enable control register      */
	    ( u_long * )CIKMF_PDCR1,	/* Port disable control register     */
	    ( u_long * )CIKMF_PICR1,	/* Port initialization control reg   */
	    ( u_long * )CIKMF_PDFQCR1,	/* Port dg free queue control reg    */
	    ( u_long * )CIKMF_PMFQCR1,	/* Port msg free queue control reg   */
	    ( u_long * )CIKMF_PMTCR1,	/* Port maintenance timer control reg*/
	    ( u_long * )CIKMF_PFAR1,	/* Port failing address register     */
	    ( u_long * )CIKMF_PESR1,	/* Port error status register	     */
	    ( u_long * )CIKMF_PPR1,	/* Port parameter register	     */
	    ( u_long * )0		/* Port parameter ext. register	     */
};
u_long	*cikmf2_regoff[] = {		/* CIKMF CI Port 2 Register Offsets  */
	    ( u_long * )0,		/* Configuration register	     */
	    ( u_long * )CIKMF_XPCSER2, 	/* XPC port specific error register*/
	    ( u_long * )CIKMF_XPCSTAT2,	/* XPC port status register	     */
	    ( u_long * )CIKMF_PMCSR2,	/* Port maintenance cntl & status reg*/
	    ( u_long * )CIKMF_PSR2,	/* Port status register		     */
	    ( u_long * )CIKMF_PQBBR2,	/* PQB base register 		     */
	    ( u_long * )CIKMF_PCQ0CR2,	/* Port command queue 0 control reg  */
	    ( u_long * )CIKMF_PCQ1CR2,	/* Port command queue 1 control reg  */
	    ( u_long * )CIKMF_PCQ2CR2,	/* Port command queue 2 control reg  */
	    ( u_long * )CIKMF_PCQ3CR2,	/* Port command queue 3 control reg  */
	    ( u_long * )CIKMF_PSRCR2,	/* Port status release control reg   */
	    ( u_long * )CIKMF_PECR2,	/* Port enable control register      */
	    ( u_long * )CIKMF_PDCR2,	/* Port disable control register     */
	    ( u_long * )CIKMF_PICR2,	/* Port initialization control reg   */
	    ( u_long * )CIKMF_PDFQCR2,	/* Port dg free queue control reg    */
	    ( u_long * )CIKMF_PMFQCR2,	/* Port msg free queue control reg   */
	    ( u_long * )CIKMF_PMTCR2,	/* Port maintenance timer control reg*/
	    ( u_long * )CIKMF_PFAR2,	/* Port failing address register     */
	    ( u_long * )CIKMF_PESR2,	/* Port error status register	     */
	    ( u_long * )CIKMF_PPR2,	/* Port parameter register	     */
	    ( u_long * )0		/* Port parameter ext. register	     */
};
u_long	*cishc_regoff[] = {		/* CISHC Register Offsets  */
	    ( u_long * )0,		/* Configuration register	     */
	    ( u_long * )0,		/* Maintenance address register      */
	    ( u_long * )0,		/* Maintenance data register	     */
	    ( u_long * )CISHC_PMCSR,	/* Port maintenance cntl & status reg*/
	    ( u_long * )CISHC_PSR,	/* Port status register		     */
	    ( u_long * )CISHC_PQBBR,	/* PQB base register 		     */
	    ( u_long * )CISHC_PCQ0CR,	/* Port command queue 0 control reg  */
	    ( u_long * )CISHC_PCQ1CR,	/* Port command queue 1 control reg  */
	    ( u_long * )CISHC_PCQ2CR,	/* Port command queue 2 control reg  */
	    ( u_long * )CISHC_PCQ3CR,	/* Port command queue 3 control reg  */
	    ( u_long * )CISHC_PSRCR,	/* Port status release control reg   */
	    ( u_long * )CISHC_PECR,	/* Port enable control register      */
	    ( u_long * )CISHC_PDCR,	/* Port disable control register     */
	    ( u_long * )CISHC_PICR,	/* Port initialization control reg   */
	    ( u_long * )CISHC_PDFQCR,	/* Port dg free queue control reg    */
	    ( u_long * )CISHC_PMFQCR,	/* Port msg free queue control reg   */
	    ( u_long * )CISHC_PMTCR,	/* Port maintenance timer control reg*/
	    ( u_long * )CISHC_PFAR,	/* Port failing address register     */
	    ( u_long * )CISHC_PESR,	/* Port error status register	     */
	    ( u_long * )CISHC_PPR,	/* Port parameter register	     */
	    ( u_long * )0		/* Port parameter ext. register	     */
};
static CLFTAB				/* Console Logging Formating Tables  */
/* NULL entries represent events which should never be logged by the CI port
 * driver.
 */
		ci_cli[] = {		/* CI Informational Event Table	     */
    { CF_RPORT,  "cable a: transitioned from bad to good" },
    { CF_RPORT,  "cable b: transitioned from bad to good" },
    { CF_RPORT,  "cables: transitioned from crossed to uncrossed" },
    { CF_LPORT,  "cable a: connectivity transitioned from bad to good" },
    { CF_LPORT,  "cable b: connectivity transitioned from bad to good" },
    { CF_INIT,   "port initialized" },
    { CF_LPORT,  "port initialized" },
    { CF_LPORT,  "port recovered power" }
},
		ci_clw[] = {		/* CI Warning Event Table	     */