sccreg.h

<B>Digital的Unix操作系统VAX 4.2源码</B>

/*
 *	@(#)sccreg.h	4.2	(ULTRIX)	8/16/90
 */

/************************************************************************
 *									*
 *			Copyright (c) 1988 by				*
 *		Digital Equipment Corporation, Maynard, MA		*
 *			All rights reserved.				*
 *									*
 *   This software is furnished under a license and may be used and	*
 *   copied  only  in accordance with the terms of such license and	*
 *   with the  inclusion  of  the  above  copyright  notice.   This	*
 *   software  or  any	other copies thereof may not be provided or	*
 *   otherwise made available to any other person.  No title to and	*
 *   ownership of the software is hereby transferred.			*
 *									*
 *   The information in this software is subject to change  without	*
 *   notice  and should not be construed as a commitment by Digital	*
 *   Equipment Corporation.						*
 *									*
 *   Digital assumes no responsibility for the use  or	reliability	*
 *   of its software on equipment which is not supplied by Digital.	*
 *									*
 ************************************************************************
 *
 * sccreg.h
 *
 * SCC SLU console driver
 *
 * Modification history
 *
 * 20-Feb-1990 - pgt (Philip Gapuz Te)
 * 	created file.
 *
 */

/* Serial line registers */
struct scc_reg {
  vu_short SCC_CMD;
  u_short pad1[1];
  vu_short SCC_DATA;
  u_short pad2[1];
};

/* saved SCC registers */
struct scc_saved_reg {
  char wr1;
  char wr3;
  char wr4;
  char wr5;
  char wr14;
};

/* IOASIC DMA registers */
struct ioc_reg {
  u_long XDMA_REG;
  long pad[3];
  u_long RDMA_REG;
};

#define CONSOLEMAJOR 0
#define NSCCLINE 4

#define SCC_KYBD  0
#define SCC_MOUSE 1
#define SCC_COMM1 2
#define SCC_COMM2 3

#define SCC0_A SCC_MOUSE
#define SCC0_B SCC_COMM1
#define SCC1_A SCC_KYBD
#define SCC1_B SCC_COMM2

#define SCC_PAGE_SIZE 4096 /* bytes */
#define SCC_HALF_PAGE 2048 
#define SCC_WORD 4

/* Driver and data specific structure */
struct	scc_softc {
  struct scc_reg *sc_regs[4];	   /* 3MIN SLU regs               */
  struct scc_saved_reg sc_saved_regs[4];
  struct ioc_reg *ioc_regs[4];  /* IOASIC DMA registers         */
  int rflag[4];                 /* flag for switching rbufs     */
  char *rbuf[4][2];          /* two receive buffers per unit */
  char *tbuf[4];             /* transmit buffers             */
  char *tptr[4];             /* transmit buffer start ptr    */
  long sc_flags[NSCCLINE];       /* Flags (one per line)		*/
  long sc_category_flags[NSCCLINE]; /* Category flags (one per line)*/
  u_long sc_softcnt[NSCCLINE];	/* Soft error count total	*/
  u_long sc_hardcnt[NSCCLINE];	/* Hard error count total	*/
  char sc_device[DEV_SIZE][NSCCLINE]; /* Device type string	*/
};

/* Baud rate support status */
struct baud_support {
  u_char baud_lo;               /* Low time constant - WR12 */
  u_char baud_hi;               /* Hi time constant - WR13 */
  u_char baud_support;          /* Set if baudrate supported */
};

/* dc7085 line control status definitions (dclcs) */
#define DC_SR		0x08		/* Secondary Receive		*/
#define DC_CTS		0x10		/* Clear To Send		*/
#define DC_CD		0x20		/* Carrier Detect		*/
#define DC_RI		0x40		/* Ring Indicate		*/
#define DC_DSR		0x80		/* Data Set Ready		*/
#define DC_LE		0x100		/* Line Enable			*/
#define DC_DTR		0x200		/* Data Terminal Ready		*/
#define DC_BRK		0x400		/* Break			*/
#define DC_ST		0x800		/* Secondary Transmit		*/
#define DC_RTS		0x1000		/* Request To Send		*/

/* DM lsr definitions */
#define SML_LE		0x01		/* Line enable			*/
#define SML_DTR		0x02		/* Data terminal ready		*/
#define SML_RTS		0x04		/* Request to send		*/
#define SML_ST		0x08		/* Secondary transmit		*/
#define SML_SR		0x10		/* Secondary receive		*/
#define SML_CTS		0x20		/* Clear to send		*/
#define SML_CAR		0x40		/* Carrier detect		*/
#define SML_RNG		0x80		/* Ring				*/
#define SML_DSR		0x100		/* Data set ready, not DM bit	*/

/* Read registers */
#define SCC_RR0             0x00            /* Tx/Rx buffer status and Ext status */
#define SCC_RR1             0x01            /* Special Recv Condition status */
#define SCC_RR2             0x02            /* Interrupt vector */
#define SCC_RR3             0x03            /* Interrupt pending (channel A only) */
#define SCC_RR8             0x08            /* Receive buffer */
#define SCC_RR10            0x0a            /* Loop/Clock status */
#define SCC_RR12            0x0c            /* Lower byte of time constant */
#define SCC_RR13            0x0d            /* Upper byte of time constant */
#define SCC_RR15            0x0f            /* External/Status interrupt enable */

/* Write registers */
#define SCC_WR0             0x00            /* Command register */
#define SCC_WR1             0x01            /* Tx/Rx interrupt and data transfer mode */
#define SCC_WR2             0x02            /* Interrupt vector */
#define SCC_WR3             0x03            /* Receive parameters and control */
#define SCC_WR4             0x04            /* Tx/Rx misc parameters and modes */
#define SCC_WR5             0x05            /* Transmit parameters and controls */
#define SCC_WR6             0x06            /* Sync char or SDLC address field */
#define SCC_WR7             0x07            /* Sync char or SDLC flag */
#define SCC_WR8             0x08            /* Transmit buffer */
#define SCC_WR9             0x09            /* Master interrupt control and reset */
#define SCC_WR10            0x0a            /* Misc Tx/Rx control bits */
#define SCC_WR11            0x0b            /* Clock mode control */
#define SCC_WR12            0x0c            /* Lower byte of BRG time constant */
#define SCC_WR13            0x0d            /* Upper byte of BRG time constant */
#define SCC_WR14            0x0e            /* Misc control bits */
#define SCC_WR15            0x0f            /* External/Status interrupt control */

/* RR0 */
#define SCC_RR0_RCHAR_AVAIL        0x01 /* Rx character available */
#define SCC_RR0_ZCOUNT             0x02 /* Zero count */
#define SCC_RR0_TBUF_EMPTY         0x04 /* Tx buffer empty */
#define SCC_RR0_DCD                0x08 /* DCD */
#define SCC_RR0_SYNC               0x10 /* SYNC */
#define SCC_RR0_HUNT               0x10 /* HUNT */
#define SCC_RR0_CTS                0x20 /* CTS */
#define SCC_RR0_TX_UNDERRUN        0x40 /* Tx underrun/EOM */
#define SCC_RR0_BREAK              0x80 /* BREAK */
#define SCC_RR0_ABORT              0x80 /* ABORT */

/* RR1 */
#define SCC_RR1_ALL_SENT           0x01 /* All sent */
#define SCC_RR1_RCODE2             0x02 /* Residue code 2 */
#define SCC_RR1_RCODE1             0x04 /* Residue code 1 */
#define SCC_RR1_RCODE0             0x08 /* Residue code 0 */
#define SCC_RR1_PE                 0x10 /* Parity error */
#define SCC_RR1_DO                 0x20 /* Rx overrun error */
#define SCC_RR1_FE                 0x40 /* Framing error */
#define SCC_RR1_CRC                0x40 /* CRC error */
#define SCC_RR1_EOF                0x80 /* End of frame (SDLC) */

/* RR3 */
#define SCC_RR3_B_EXT_IP           0x01 /* Channel B Ext/Stat IP */
#define SCC_RR3_B_TIP              0x02 /* Channel B Tx IP */
#define SCC_RR3_B_RIP              0x04 /* Channel B Rx IP */
#define SCC_RR3_A_EXT_IP           0x08 /* Channel A Ext/Stat IP */
#define SCC_RR3_A_TIP              0x10 /* Channel A Tx IP */
#define SCC_RR3_A_RIP              0x20 /* Channel A Rx IP */

/* RR10 */