fgreg.h

<B>Digital的Unix操作系统VAX 4.2源码</B>

/*
 * 	@(#)fgreg.h	4.1	(ULTRIX)	7/2/90
 */

/************************************************************************
 *									*
 *			Copyright (c) 1986 by				*
 *		Digital Equipment Corporation, Maynard, MA		*
 *			All rights reserved.				*
 *									*
 *   This software is furnished under a license and may be used and	*
 *   copied  only  in accordance with the terms of such license and	*
 *   with the  inclusion  of  the  above  copyright  notice.   This	*
 *   software  or  any	other copies thereof may not be provided or	*
 *   otherwise made available to any other person.  No title to and	*
 *   ownership of the software is hereby transferred.			*
 *									*
 *   This software is  derived  from  software  received  from  the	*
 *   University	of   California,   Berkeley,   and   from   Bell	*
 *   Laboratories.  Use, duplication, or disclosure is  subject  to	*
 *   restrictions  under  license  agreements  with  University  of	*
 *   California and with AT&T.						*
 *									*
 *   The information in this software is subject to change  without	*
 *   notice  and should not be construed as a commitment by Digital	*
 *   Equipment Corporation.						*
 *									*
 *   Digital assumes no responsibility for the use  or	reliability	*
 *   of its software on equipment which is not supplied by Digital.	*
 *									*
 ************************************************************************/

/***********************************************************************
 *
 * Modification History:
 *
 * 23-Sep-88 -- carito (Allen Carito)
 *      Added fgctsi structure.  This structure describes the extended
 *      driver state area used by the LEGSS Firmware.
 *
 * 22-Jan-88  -- rafiey (Ali Rafieymehr)
 *	Created this header file for the Firefox driver.
 *	Derived from qdreg.h.
 *
 **********************************************************************/

/* Dragon ADDER reg map */
/* ADDER register bit definitions */
/* Y_SCROLL_CONSTANT */

#define SCROLL_ERASE		0x2000
#define ADDER_SCROLL_DOWN	0x1000

/*******************************************************************************/
/* A CHIP Control Status Register bits */

#define	OP_DONE			0x0001

/* FBIC registers + bit definitions */

#define	FGSAVGPR	0x071	/* scratch register for halt code */
#define	FGWHAMI		0x077	/* Unique software ID register */
#define	FBICSR	0x07A		/* FBIC control status register */

#define HALT_ENB	0x00000080  
#define BIT_13		0x00002000
#define	HALTCPU		0x02000000
#define	RESET		0x01000000
#define	IRQC2M		0x000F0000
#define	NORMAL_MODE	0x0000003E   /* Normal mode */

/* Tchip registers + bit definitions */

#define	TCHIP_UNBLANK	0x800		/* unblank */

/* DCHIP constants */

/* Values for the SETUP_* registers */

/* Which color channel */

#define	RED_PLANE	0x0000
#define	GREEN_PLANE	0x0200
#define	BLUE_PLANE	0x0400

/* Color channel nibble */

#define	HIGH_NIBBLE	0x00010100 /* Also respond to dest. register reads */
#define	NO_LOW_NIBBLE	0x4000	/* for 4 or 12 plane system */

/* Nibble of longword during Z-cycles */

#define	Z_NIBBLE_0	0x0000
#define	Z_NIBBLE_1	0x0800
#define	Z_NIBBLE_2	0x1000
#define	Z_NIBBLE_3	0x1800
#define	Z_NIBBLE_4	0x2000
#define	Z_NIBBLE_5	0x2800

/* Nibble of longword during direct bitmap access in "I" mode.
 * Affects the Write_mask as well.  It basicly determines the
 * logical plane number.
*/

#define	I_NIBBLE_0	0x0000
#define	I_NIBBLE_1	0x0001
#define	I_NIBBLE_2	0x0002
#define	I_NIBBLE_3	0x0003
#define	I_NIBBLE_4	0x0004
#define	I_NIBBLE_5	0x0005
#define	I_NIBBLE_6	0x0006
#define	I_NIBBLE_15	0x000F

#define	MASTER_DCHIP	0x00020000	/* respond to source register reads */

/* TCHIP bit definitions */

/* TCHIP CSR bits */

#define UNBLANK         0x0800
#define WC_LOAD         0x0001
#define VDAC_LOAD       0x0002
#define PMAP_LOAD       0x0004
#define ONE_LOAD        0x0008
#define COLLECT_VDAC0   0x0120
#define COLLECT_VDAC1   0x0160
#define COLLECT_VDAC2   0x01A0

/* INTERRUPT bits */

#define PVI_IRQ 1
#define VBS_IRQ 2
#define VBF_IRQ 4

#define       LF_ONE          15
#define       LF_ZERO          0

/*******************************************************************************/
/* ADDER status and interrupt enable registers [1], [2], [3] */

#define DISABLE 		0x0000
#define PAUSE_COMPLETE		0x0001
#define FRAME_SYNC		0x0002
#define INIT_COMPLETE		0x0004
#define RASTEROP_COMPLETE	0x0008

#define ADDRESS_COMPLETE	0x0010
#define RX_READY		0x0020
#define TX_READY		0x0040
#define ID_SCROLL_READY 	0x0080

#define TOP_CLIP		0x0100
#define BOTTOM_CLIP		0x0200
#define LEFT_CLIP		0x0400
#define RIGHT_CLIP		0x0800
#define NO_CLIP 		0x1000
#define VSYNC			0x2000

/* ADDER command register [8], [10] */

#define OCR_zero		0x0000
#define Z_BLOCK0		0x0000
#define OCRA			0x0000
#define OCRB			0x0004
#define RASTEROP		0x02c0
#define PBT			0x03c0
#define BTPZ			0x0bb0
#define PTBZ			0x07a0
#define DTE			0x0400
#define S1E			0x0800
#define S2E			0x1000
#define VIPER_Z_LOAD		0x01A0
#define ID_LOAD 		0x0100
#define CANCEL			0x0000
#define LF_R1			0x0000
#define LF_R2			0x0010
#define LF_R3			0x0020
#define LF_R4			0x0030

/* ADDER rasterop mode register [9] */

#define NORMAL			0x0000
#define LINEAR_PATTERN		0x0002
#define X_FILL			0x0003
#define Y_FILL			0x0007
#define BASELINE		0x0008
#define HOLE_ENABLE		0x0010
#define SRC_1_INDEX_ENABLE	0x0020
#define DST_INDEX_ENABLE	0x0040
#define DST_WRITE_ENABLE	0x0080

/* ADDER source 2 size register */

#define NO_TILE 		0x0080

/* External registers base addresses */

#define CS_UPDATE_MASK		0x0060
#define CS_SCROLL_MASK		0x0040

/* VIPER registers */

#define RESOLUTION_MODE 	0x0080
#define MEMORY_BUS_WIDTH	0x0081
#define PLANE_ADDRESS		0x0083
#define LU_FUNCTION_R1		0x0084
#define LU_FUNCTION_R2		0x0085
#define LU_FUNCTION_R3		0x0086
#define LU_FUNCTION_R4		0x0087
#define MASK_1			0x0088
#define MASK_2			0x0089
#define SOURCE			0x008a
#define SOURCE_Z		0x0000
#define BACKGROUND_COLOR	0x008e
#define BACKGROUND_COLOR_Z	0x000C
#define FOREGROUND_COLOR	0x008f
#define FOREGROUND_COLOR_Z	0x0004
#define SRC1_OCR_A		0x0090
#define SRC2_OCR_A		0x0091
#define DST_OCR_A		0x0092
#define SRC1_OCR_B		0x0094
#define SRC2_OCR_B		0x0095
#define DST_OCR_B		0x0096

/* VIPER scroll registers */

#define SCROLL_CONSTANT 	0x0082
#define SCROLL_FILL		0x008b
#define SCROLL_FILL_Z		0x0008
#define LEFT_SCROLL_MASK	0x008c
#define RIGHT_SCROLL_MASK	0x008d

/* VIPER register bit definitions */

#define EXT_NONE		0x0000
#define EXT_SOURCE		0x0001
#define EXT_M1_M2		0x0002
#define INT_NONE		0x0000
#define INT_SOURCE		0x0004
#define INT_M1_M2		0x0008
#define ID			0x0010
#define NO_ID			0x0000
#define WAIT			0x0020
#define NO_WAIT 		0x0000
#define BAR_SHIFT_DELAY 	WAIT
#define NO_BAR_SHIFT_DELAY	NO_WAIT


/* VIPER logical function unit codes */

#define LF_ZEROS		0x0000
#define LF_D_XOR_S		0x0006
#define LF_SOURCE		0x000A
#define LF_D_OR_S		0x000E
#define LF_ONES 		0x000F
#define INV_M1_M2		0x0030
#define FULL_SRC_RESOLUTION	0X00C0 /* makes second pass like first pass */

/* VIPER scroll register [2] */

#define SCROLL_DISABLE		0x0040
#define SCROLL_ENABLE		0x0020
#define VIPER_LEFT		0x0000
#define VIPER_RIGHT		0x0010
#define VIPER_UP		0x0040
#define VIPER_DOWN		0x0000

/* Adder scroll register */

#define ADDER_UP		0x0000
#define ADDER_DOWN		0x1000

/* Misc scroll definitions */

#define UP		0
#define DOWN		1
#define LEFT		2
#define RIGHT		3
#define NODIR		4
#define SCROLL_VMAX	31
#define SCROLL_HMAX	15
#define NEW		2
#define OLD		1
#define BUSY		1
#define DRAG		1
#define SCROLL		0

/* VDAC color map entries */

#define VDAC_BLACK	0x0000
#define	VDAC_BLUE	0x00F0
#define	VDAC_GREEN	0x0F00
#define	VDAC_CYAN	0x0FF0
#define	VDAC_RED	0x000F
#define	VDAC_MAGENTA	0x00FF
#define	VDAC_YELLOW	0x0F0F
#define	VDAC_WHITE	0x0FFF
#define	VDAC_GREY_1	0x0000
#define	VDAC_GREY_2	0x0424
#define	VDAC_GREY_3	0x0848
#define	VDAC_GREY_4	0x0C6C
#define	VDAC_GREY_5	0x0090
#define	VDAC_GREY_6	0x04B4
#define	VDAC_GREY_7	0x08D8
#define	VDAC_GREY_8	0x0FFF

/* miscellaneous defines */

#define ALL_PLANES	0xffffffff
#define UNITY		0x1fff		 /* Adder scale factor */
#define MAX_SCREEN_X	1280
#define MAX_SCREEN_Y	1024
#define FONT_HEIGHT	32

	struct achip {

	    /* A chip registers */

	    u_long achip_csr;		/* A chip Control Status Register */
	    u_long achip_counter;	/* A chip counter register */
            u_long achip_alpha_cntl;   	/* A chip alpha control register */
            u_long achip_int_mask1;    	/* A chip interrupt mask reg1 */
            u_long achip_int_mask2;    	/* A chip interrupt mask reg2 */
            u_long achip_int_mask3;    	/* A chip interrupt mask reg3 */
            u_long achip_clr_bits;     	/* A chip clear bits register */
            u_long achip_set_bits;     	/* A chip set bits register */
	    u_long pad1[9];
            u_long achip_x_a;		/* A chip X address register */
            u_long achip_y_a;		/* A chip Y address register */
	    u_long pad2[2];
            u_long achip_x_i;		/* A chip X increment register */
            u_long achip_y_i;		/* A chip Y increment register */
	    u_long pad3[2];
            u_long achip_x_size;       	/* A chip X size register */
            u_long achip_y_size;       	/* A chip Y size register */
	    u_long pad4[38];
            u_long achip_x_offset_src; 	/* A chip X offset SRC register */
            u_long achip_y_offset_src; 	/* A chip Y offset SRC register */
	    u_long pad5;
            u_long achip_x_offset_dst; 	/* A chip X offset DST register */
	    u_long pad6[3];
            u_long achip_y_offset_dst; 	/* A chip Y offset DST register */
	    u_long pad7[8];
            u_long achip_width_src;    	/* A chip SRC width register */
            u_long achip_width_dst;    	/* A chip DST width register */
	    u_long pad8;
            u_long achip_offset_src;   	/* A chip SRC offset register */
	    u_long pad9[3];
            u_long achip_offset_dst;   	/* A chip DST offset register */
	    u_long pad10[8];
            u_long achip_clip_x_1;     	/* A chip Clip registers */
            u_long achip_clip_y_1;     	/* A chip Clip registers */
	    u_long pad11;
            u_long achip_clip_x_2;     	/* A chip Clip registers */
	    u_long pad12[3];
            u_long achip_clip_y_2;     	/* A chip Clip registers */
	};



	struct dchip {

	    /* D chip registers */

	    u_long dchip_setup_0;	/* D chip setup register 0 */
	    u_long dchip_setup_1;	/* D chip setup register 1 */
	    u_long dchip_setup_2;	/* D chip setup register 2 */
	    u_long dchip_setup_3;	/* D chip setup register 3 */