ubareg.h

<B>Digital的Unix操作系统VAX 4.2源码</B>

	u_char	nb_pad29[3];
	u_char	nb_cur_stat;		/* (ro) Current bus status register */
#define	nb_scs_sel_ena	nb_scs_cur_stat	/* (wo) Select enable register */
	u_char	nb_pad30[3];
	u_char	nb_scs_status;		/* (ro) Bus and status register */
#define	nb_scs_dma_send	nb_scs_status	/* (wo) Start DMA send action */
	u_char	nb_pad31[3];
	u_char	nb_scs_in_data;		/* (ro) Input data regsiter */
#define	nb_scs_data_trcv nb_scs_in_data	/* (wo) Start DMA target receive action */
	u_char	nb_pad32[3];
	u_char	nb_scs_dma_ircv;	/* (wo) Start DMA initiator rcv action */
#define	nb_scs_reset nb_scs_dma_ircv	/* (ro) Reset interrupt/error action */
	u_char	nb_pad33[3];
	union {				/* DMA address register */
		u_char	c[4];		/* 8-bit (wo) compatability mode */
		u_long	l;		/* 32-bit (rw) extended mode */
	} nb_scd_adr;
	u_long	nb_pad35[7];
	union {				/* DMA byte count register */
		u_short	w[2];		/* 16-bit (r/w) compatability mode */
		u_long	l;		/* 32-bit (r/w) extended mode */
	} nb_scd_cnt;
	u_char	nb_scd_dir;		/* (wo) DMA transfer direction */
	u_char	nb_pad37[3];
	u_long	nb_pad64[6];
	u_char	nb_stc_mode;		/* Storage controller mode */
					/* (CVAXSTAR only) */
	u_char	nb_pad65[3];
	u_long	nb_pad38[16327];
	u_char	nb_ddb[16384];		/* Disk cntlr - data buffer RAM */
	u_long	nb_pad39[12288];
	u_short	nb_ni_rdp;		/* Network cntlr register data port */
	u_short	nb_pad40;
	u_short	nb_ni_rap;		/* Network cntlr register address port */
	u_short	nb_pad41;
	u_long	nb_pad42[16382];
	u_short	nb_cur_cmd;		/* Cursor command register */
	u_short	nb_pad43;
	u_short	nb_cur_xpos;		/* Cursor X position */
	u_short	nb_pad44;
	u_short	nb_cur_ypos;		/* Cursor Y position */
	u_short	nb_pad45;
	u_short	nb_cur_xmin_1;		/* Region 1 left edge */
	u_short	nb_pad46;
	u_short	nb_cur_xmax_1;		/* Region 1 right edge */
	u_short	nb_pad47;
	u_short	nb_cur_ymin_1;		/* Region 1 top edge */
	u_short	nb_pad48;
	u_short	nb_cur_ymax_1;		/* Region 1 bottom edge */
	u_short	nb_pad49;
	u_long	nb_pad50[4];
	u_short	nb_cur_xmin_2;		/* Region 2 left edge */
	u_short	nb_pad51;
	u_short	nb_cur_xmax_2;		/* Region 2 right edge */
	u_short	nb_pad52;
	u_short	nb_cur_ymin_2;		/* Region 2 top edge */
	u_short	nb_pad53;
	u_short	nb_cur_ymax_2;		/* Region 2 bottom edge */
	u_short	nb_pad54;
	u_short	nb_load;		/* Cursor sprite pattern load */
	u_short	nb_pad55;
	u_long	nb_pad56[16368];
	u_long	nb_ni_rom[32768];		/* Network option board ROM */
	u_long	nb_pad57[32768];
	u_long	nb_vo_rom[65536];		/* Video option board ROM */
};

struct	nb2_regs {
	u_long	nb_bitmap[65536];		/* Monochrome video RAM */
						/* VS410=128kb   VS420=256kb */
};

/* TODO: need to map 128KB disk buffer */
/*
struct	nb3_regs {
	u_long	nb_co_map[0x8000000];		/* Video option board (color) */
/*
};
*/
struct	nb4_regs {
	u_long	mct_base;	/* Phys. addr. of main configuration. table */
	u_long	option1;	/* Phys. addr. of first option's firmware */
	u_long	option2;	/* Phys. addr. of second option's firmware */
	u_long	good64kb;	/* Phys. addr. of good main memory */
	u_long	bitmap;		/* Phys. addr. of memory bitmap */
	u_long	bitmap_length;	/* Length of memory bitmap in bytes */
	u_long	kb_good;	/* Status of LK201 keyboard */
	u_long	mouse_good;	/* Status of pointer device (mouse or tablet) */
	u_long	init_output;	/* Phys. addr. of init routine for console out*/
	u_long	reset_output;	/* Phys. addr.of reset routine for console out*/
	u_long	init_input;	/* Phys. addr. of init routine for console in */
	u_long	reset_input;	/* Phys. addr.of reset routine for console in */
	u_long	get_char;	/* Phys. addr.of "get_char" routine */
	u_long	put_char;	/* Phys. addr.of "put_char" routine */
	u_long	fbeep;		/* Phys. addr.of "beep" routine */
	u_long	cursor_max_row;	/* Max. char. row of console window rect. */
	u_long	cursor_column;	/* Current horizontal pos. */
	u_long	cursor_row;	/* Current vertical pos. */
	u_long	save_console;	/* Phys. addr. of save routine */
	u_long	restore_console;/* Phys. addr. of restore routine */
	u_long	st_flags;	/* System firmware selftest control word */
	u_long	st_loop_addr;	/* System firmware selftest loop address */
	u_long  pad1[94];       /* Undefined */
	u_long  vmb_version;    /* VMB version number */
	u_long  self_test_ver;  /* Self-test version */
	u_long  console_ver;    /* Console version */
};

/*
 * FireFox registers
 */
struct  nb5_regs {
        u_long  nb_legss[0x2000000];  /* Firefox LEGSS */
};

#endif /* LOCORE */

/* qb_mser */
#define	QBM_CD		0x300		/* memory error code	*/
#define QBM_NXM		0x80		/* nonexistant memory	*/
#define QBM_LPE		0x40		/* local memory parity	*/
#define QBM_QPE		0x20		/* q-bus parity error	*/
#define QBM_DMAQPE	0x10		/* dma q-bus parity	*/
#define QBM_LEB		0x8		/* lost error bit	*/
#define QBM_WRW		0x2		/* write wrong parity	*/
#define QBM_PENB	0x1		/* parity enable	*/
#define QBM_EMASK	0xf8		/* mask to isolate cause*/

/* toy csr */
#define QBT_UIP		0x80		/* update in progress	*/
#define QBT_SETA	0x20		/* set up divider	*/
#define	QBT_SETUP	0x80		/* stop			*/
#define QBT_SETB	0x6		/* binary and 24 hour	*/

/* uba_cnfgr */
#define	UBACNFGR_UBINIT	0x00040000	/* unibus init asserted */
#define	UBACNFGR_UBPDN	0x00020000	/* unibus power down */
#define	UBACNFGR_UBIC	0x00010000	/* unibus init complete */

/* uba_cr */
#define	UBACR_MRD16	0x40000000	/* map reg disable bit 4 */
#define	UBACR_MRD8	0x20000000	/* map reg disable bit 3 */
#define	UBACR_MRD4	0x10000000	/* map reg disable bit 2 */
#define	UBACR_MRD2	0x08000000	/* map reg disable bit 1 */
#define	UBACR_MRD1	0x04000000	/* map reg disable bit 0 */
#define	UBACR_IFS	0x00000040	/* interrupt field switch */
#define	UBACR_BRIE	0x00000020	/* BR interrupt enable */
#define	UBACR_USEFIE	0x00000010	/* UNIBUS to SBI error field IE */
#define	UBACR_SUEFIE	0x00000008	/* SBI to UNIBUS error field IE */
#define	UBACR_CNFIE	0x00000004	/* configuration IE */
#define	UBACR_UPF	0x00000002	/* UNIBUS power fail */

/* uba_sr */
#define	UBASR_BR7FULL	0x08000000	/* BR7 receive vector reg full */
#define	UBASR_BR6FULL	0x04000000	/* BR6 receive vector reg full */
#define	UBASR_BR5FULL	0x02000000	/* BR5 receive vector reg full */
#define	UBASR_BR4FULL	0x01000000	/* BR4 receive vector reg full */
#define	UBASR_RDTO	0x00000400	/* UNIBUS to SBI read data timeout */
#define	UBASR_RDS	0x00000200	/* read data substitute */
#define	UBASR_CRD	0x00000100	/* corrected read data */
#define	UBASR_CXTER	0x00000080	/* command transmit error */
#define	UBASR_CXTMO	0x00000040	/* command transmit timeout */
#define	UBASR_DPPE	0x00000020	/* data path parity error */
#define	UBASR_IVMR	0x00000010	/* invalid map register */
#define	UBASR_MRPF	0x00000008	/* map register parity failure */
#define	UBASR_LEB	0x00000004	/* lost error */
#define	UBASR_UBSTO	0x00000002	/* UNIBUS select timeout */
#define	UBASR_UBSSYNTO	0x00000001	/* UNIBUS slave sync timeout */

#define	UBASR_BITS \
"\20\13RDTO\12RDS\11CRD\10CXTER\7CXTMO\6DPPE\5IVMR\4MRPF\3LEB\2UBSTO\1UBSSYNTO"

/* uba_brrvr[] */
#define	UBABRRVR_AIRI	0x80000000	/* adapter interrupt request */
#define	UBABRRVR_DIV	0x0000ffff	/* device interrupt vector field */
 
/* uba_dpr */
#define	UBADPR_BNE	0x80000000	/* buffer not empty - purge */
#define	UBADPR_BTE	0x40000000	/* buffer transfer error */
#define	UBADPR_DPF	0x20000000	/* DP function (RO) */
#define	UBADPR_BS	0x007f0000	/* buffer state field */
#define	UBADPR_BUBA	0x0000ffff	/* buffered UNIBUS address */
#define	UBA_PURGE780(uba, bdp){ \
	((uba)->uba_dpr[bdp] |= UBADPR_BNE);\
}


#define	UBACR_ADINIT	0x00000001	/* adapter init */

#define	UBADPR_ERROR	0x80000000	/* error occurred */
#define	UBADPR_NXM	0x40000000	/* nxm from memory */
#define	UBADPR_UCE	0x20000000	/* uncorrectable error */
#define	UBADPR_PURGE	0x00000001	/* purge bdp */
/* the DELAY is for a hardware problem */
#define	UBA_PURGE750(uba, bdp) { \
    ((uba)->uba_dpr[bdp] |= (UBADPR_PURGE|UBADPR_NXM|UBADPR_UCE)); \
    DELAY(8); \
}

#define	BUA_PURGE8200(uba, bdp) { \
    (((struct bua_regs *) uba)->bua_dpr[bdp] |= (BUADPR_PURGE)); \
}

/*
 * Macros for fast buffered data path purging in time-critical routines.
 *
 * Too bad C pre-processor doesn't have the power of LISP in macro
 * expansion...
 */

#define	UBAPURGE(uba, bdp, ubanum) { \
	int ubatype = uba_hd[ubanum].uba_type; \
	if(ubatype&UBABUA) BUA_PURGE8200((uba), (bdp)) \
	if(ubatype&UBA780) UBA_PURGE780((uba), (bdp)) \
	if(ubatype&UBA750) UBA_PURGE750((uba), (bdp)) \
}


/* uba_mr[] */
#define	UBAMR_MRV	0x80000000	/* map register valid */
#define	UBAMR_BO	0x02000000	/* byte offset bit */
#define	UBAMR_DPDB	0x01e00000	/* data path designator field */
#define	UBAMR_SBIPFN	0x000fffff	/* SBI page address field */

#define	UBAMR_DPSHIFT	21		/* shift to data path designator */

/*
 * Number of UNIBUS map registers.  We can't use the last 8k of UNIBUS
 * address space for i/o transfers since it is used by the devices,
 * hence have slightly less than 256K of UNIBUS address space.
 */
#define	NUBMREG	496
/*
 * Number of Q-BUS mapping registers. We actually use just the first 496
 * because the device drivers know about the format of ubinfo which is
 * based on an 18-bit unibus address. To change this would require changes
 * to most of the device drivers.
 */
#define QBMREG 8192
/*
 * All systems now have an 8k csr space. If this changes it should be put
 * into cpusw or some other structure.
 */
#define DEVSPACESIZE 8192

/*
 * Number of unibus buffered data paths and possible uba's per cpu type.
 */

#define NBDP8200 5
#define NBDP8800 5
#define	NBDP8600	15
#define	NBDP780	15
#define	NBDP750	3
#define	NBDP730	0
#define NBDPUVI 0
#define	MAXNBDP	15

#define NUBA8600 8
#define NUBA8200 10
#define NUBA8800 10
#define NUBA780 4
#define	NUBA750	1
#define	NUBA730	1
#define NUBAUVI 1

/*
 * Symbolic BUS addresses for UBAs and QBUSes.
 *
 */

#define	UMEM730		((u_short *)(0xfc0000))
#define UMEMSIZE730	(512*496)
#define UDEVADDR730	((u_short *)(0xfc0000+0760000))

#define	UMEM750(i)	((u_short *)(0xfc0000-(i)*0x40000))
#define UMEMSIZE750	(512*496)
#define UDEVADDR750(i)	((u_short *)(0xfc0000-(i)*0x40000+0760000))

#define	UMEM780(i)	((u_short *)(0x20100000+(i)*0x40000))
#define UMEMSIZE780	(512*496)
#define UDEVADDR780(i)	((u_short *)(0x20100000+(i)*0x40000+0760000))

#define	UMEM8200(i)	((u_short *)(0x20400000+(i)*0x40000))
#define UMEMSIZE8200	(512*496)
#define UDEVADDR8200(i)	((u_short *)(0x20400000+(i)*0x40000+0760000))

#define	UMEM8800(io,i)	((u_short *)(0x20400000+(i)*0x40000+(io<<25)))
#define UMEMSIZE8800	(512*496)
#define UDEVADDR8800(io,i) ((u_short *)(0x20400000+(i)*0x40000+0760000+(io<<25)))

#define	UMEM8600(io,i)	((u_short *)(0x20100000+(i)*0x40000+(io<<25)))
#define UMEMSIZE8600	(512*496)
#define UDEVADDR8600(io,i) ((u_short *)(0x20100000+(i)*0x40000+0760000+(io<<25)))

#define UMEMSIZE9000	(512*496)

#define QMEMUVI		((char *)(0))
#define QMEMUVII	((char *)(0x30000000))
/*
 * Following allows VAXstar to use the QMEMmap
 * to access the second chunk if its I/O space.
 */
#define	QMEMVAXSTAR	((char *)(0x200c0000))
#define	QMEMSIZEVS	0xc0000
/*
 * Maps third chunk of VAXstar I/O space.
 */
#define	NMEMVAXSTAR	((char *)(0x30000000))
#define	NMEMSIZEVS	0x20000
#define	NMEMSIZECVS	0x40000
/*
 * Maps fourth chunk of VAXstar I/O space,
 * size may grow for color option.
 */
#define	SGMEMVAXSTAR	((char *)(0x3c000000))
#define	SGMEMSIZEVS	0x18000
/*
 * Maps fifth chunk of VAXstar I/O space,
 * for MicroVAX 2000 serial line expander.
 */
#define	SHMEMVAXSTAR	((char *)(0x38000000))
#define	SHMEMSIZEVS	0x200
/*
 * Map for FireFox I/O space
 */
#define NMEMFG          ((char *)(0x3e000000))
#define NMEMSIZEFG      0x2000000
/*
 * TODO:
 * CVAXstar 2nd level cache data storage mapping
 */
#define	CVSCACHEADDR	((char *)0x10000000)
#define	CVSCACHESIZE	0x8000
/*
 * TODO: ext mode temp, disk data buffer
 */
#define	CVSEDDBADDR	((char *)0x202d0000)
#define	CVSEDDBSIZE	0x20000
/*
 * Maps CVAXstar (VAX420) SCSI registers.
 */
#define	SZMEMCVAXSTAR	((char *)(0x200c0000))
#define	SZMEMSIZECVS	0x400
/*
 * The q-bus memory size is 4 meg plus the space for the csr's
 */
#define QMEMSIZEUVI	(512*8192)
#define QDEVADDRUVI	((u_short *)(0x20000000))

/*
 * Macro to offset a UNIBUS device address, often expressed as
 * something like 0172520 by forcing it into the last 8K of UNIBUS memory
 * space.
 */
#define	ubdevreg(addr)	((addr)&017777)

/* set aside 512 map registers (the first ones) for backward compat. with
 * ubasetup() calls.
 */
#define QBNOTUB 512
#define QBREGMASK	0x1fff
#define NQBREGMASK 	0x3ff