uu.c

<B>Digital的Unix操作系统VAX 4.2源码</B>

#ifndef lint
static char *sccsid = "@(#)uu.c	4.1	(ULTRIX)	7/2/90";
#endif lint
/************************************************************************
 *									*
 *			Copyright (c) 1985 by				*
 *		Digital Equipment Corporation, Maynard, MA		*
 *			All rights reserved.				*
 *									*
 *   This software is furnished under a license and may be used and	*
 *   copied  only  in accordance with the terms of such license and	*
 *   with the  inclusion  of  the  above  copyright  notice.   This	*
 *   software  or  any  other copies thereof may not be provided or	*
 *   otherwise made available to any other person.  No title to and	*
 *   ownership of the software is hereby transferred.			*
 *									*
 *   This software is  derived  from  software  received  from  the	*
 *   University    of   California,   Berkeley,   and   from   Bell	*
 *   Laboratories.  Use, duplication, or disclosure is  subject  to	*
 *   restrictions  under  license  agreements  with  University  of	*
 *   California and with AT&T.						*
 *									*
 *   The information in this software is subject to change  without	*
 *   notice  and should not be construed as a commitment by Digital	*
 *   Equipment Corporation.						*
 *									*
 *   Digital assumes no responsibility for the use  or  reliability	*
 *   of its software on equipment which is not supplied by Digital.	*
 *									*
 ************************************************************************/
/*	uu.c	6.1	83/07/29	*/

#include "uu.h"
#if NUU > 0 || defined(BINARY)
/*
 * TU58 DECtape II/DL11 device driver
 *
 * The TU58 is treated as a block device (only).  Error detection and
 * recovery is not very extensive, but sufficient to handle the most
 * common errors. It is assumed that the TU58 will follow the RSP 
 * protocol exactly, very few protocol errors are checked for.  
 *
 * To reduce interrupt latency, `options UUDMA' should be specified 
 * in the config file to make sure the `pseudo-DMA' code in locore.s
 * will be compiled into the system. Otherwise overrun errors will 
 * occur frequently (these errors are not reported).
 *
 * TODO:
 *
 * - Add ioctl code to wind/rewind cassette
 * 18-mar-86  -- jaw     br/cvec changed to NOT use registers.
 *
 *
 */

#include "../data/uu_data.c"

#if defined(VAX750) || defined(VAX730)
extern char *tustates[];
#else
char *tustates[TUS_NSTATES] = {
	"INIT1", "INIT2", "IDLE", "SENDH", "SENDD", "SENDC", "SENDR",
	"SENDW", "GETH", "GETD", "GETC", "GET", "WAIT", "RCVERR", "CHKERR"
};
#endif

#define	UNIT(dev)	(minor(dev)>>1)

u_char	uunull[2] = { 0, 0 };		/* nulls to send for initialization */
u_char	uuinit[2] = { TUF_INITF, TUF_INITF };	/* inits to send */


int uuprobe(), uuattach(), uurintr(), uuxintr(), uuwatch();
u_short uustd[] = { 0176500 };
struct uba_driver uudriver =
    { uuprobe, 0, uuattach, 0, uustd, "uu", uudinfo };

int	uuwstart;
int	uuwake();

/*ARGSUSED*/
uuprobe(reg)
	caddr_t reg;
{
	struct uudevice *uuaddr = (struct uudevice *)reg;

#ifdef lint
	uurintr(0); uuxintr(0);
#endif
	uuaddr->tcs = UUCS_INTR;
	DELAY(1000);
	uuaddr->tcs = 0;
	cvec -= 4;		/* since we are using the xmitter intrpt */
	return(sizeof (*uuaddr));
}

uuattach(ui)
	register struct uba_device *ui;
{
}

/*ARGSUSED1*/
uuopen(dev, flag)
	dev_t dev;
	int flag;	
{
	register struct uba_device *ui;
	register struct uu_softc *uuc;
	register struct uudevice *uuaddr;
	int ctlr, unit = UNIT(dev), s;

	ctlr = unit / NDPC;
	if (unit >= nNUX || (ui = uudinfo[ctlr]) == 0 || ui->ui_alive == 0)
		return (ENXIO);
	uuc = &uu_softc[ctlr];
	if (uuc->tu_dopen[unit&UMASK])
		return (EBUSY);
	if (uuwstart++ == 0)
		timeout(uuwatch, (caddr_t)0, hz);

	uuc->tu_dopen[unit&UMASK]++;
	uuaddr = (struct uudevice *)ui->ui_addr;
	s = splx(UUIPL);
	/*
	 * If the other device on this controller
	 * is already active, no need to initialize
	 */
	if (uuc->tu_dopen[0] && uuc->tu_dopen[1])
		goto ok;

	/*
	 * If the unit already initialized,
	 * just enable interrupts and return.
	 */
	if (uuc->tu_state == TUS_IDLE) {
		uuaddr->rcs = UUCS_INTR;
		goto ok;
	}

	/* 
	 * Must initialize, reset the cassette
	 * and wait for things to settle down.
	 */
	uureset(ctlr);
	sleep((caddr_t)uuc, PZERO+1);
	uitab[ctlr].b_active = NULL;
	if (uuc->tu_state != TUS_IDLE) {
		uuc->tu_state = TUS_INIT1;
		uuc->tu_dopen[unit&UMASK] = 0;
		uuc->tu_rcnt = uuc->tu_wcnt = 0;
		uuaddr->rcs = 0;
		uuaddr->tcs = 0;
		splx(s);
		return (EIO);
	}
ok:
	splx(s);
	return (0);
}

/*
 * Wait for all outstanding IO on this drive
 * complete, before closing. If both drives on
 * this controller are idle, mark the controller
 * `inactive'.
 */

uuclose(dev, flag)
	dev_t dev;
	int flag;
{
	int s, unit = UNIT(dev);
	register struct uu_softc *uuc = &uu_softc[unit/NDPC];
	struct buf *bp, *last = NULL;
	struct uudevice *uuaddr = (struct uudevice *)uudinfo[unit/NDPC]->ui_addr;

	s = splx(UUIPL);
	while (uu_pcnt[unit])
		sleep(&uu_pcnt[unit], PRIBIO);
	/*
	 * No more writes are pending, scan the 
	 * buffer queue for oustanding reads from
	 * this unit.
	 */
	for (bp = uitab[unit/NDPC].b_actf; bp; bp = bp->b_actf) {
		if (bp->b_dev == dev)
			last = bp;
	}
	if (last) {
		last->b_flags |= B_CALL;
		last->b_iodone = uuwake;
		sleep((caddr_t)last, PRIBIO);
	}
	uuc->tu_dopen[unit&UMASK] = 0;
	if (!uuc->tu_dopen[0] && !uuc->tu_dopen[1]) {
		uuc->tu_flag = 0;
		uuaddr->rcs = 0;
	}
	splx(s);
}

uuwake(bp)
	struct buf *bp;
{
	wakeup(bp);
}

uureset(ctlr)
	int ctlr;
{
	register struct uu_softc *uuc = &uu_softc[ctlr];
	register struct packet *cmd = &uucmd[ctlr];
	struct uba_device *ui = uudinfo[ctlr];
	register struct uudevice *uuaddr = (struct uudevice *)ui->ui_addr;

	uitab[ctlr].b_active++;
	uuc->tu_state = TUS_INIT1;
	uuc->tu_wbptr = uunull;
	uuc->tu_wcnt = sizeof (uunull);
	uuc->tu_rcnt = 0;
	cmd->pk_flag = TUF_CMD;
	cmd->pk_mcount = sizeof (*cmd) - 4;
	cmd->pk_mod = 0;
	cmd->pk_seq = 0;
	cmd->pk_sw = 0;
	uuaddr->rcs = 0;
	uuaddr->tcs = UUCS_INTR | UUCS_BREAK;
	uuxintr(ctlr);				/* start output */
}

/*
 * Strategy routine for block I/O
 */
uustrategy(bp)
	register struct buf *bp;
{
	register struct buf *uutab;
	struct uba_device *ui;
	int s, unit = UNIT(bp->b_dev);

	if ((unit > nNUX) || (bp->b_blkno >= NTUBLK))
		goto bad;
	ui = uudinfo[unit/NDPC];
	if (ui == 0 || ui->ui_alive == 0)
		goto bad;
	uutab = &uitab[unit/NDPC];	/* one request queue per controller */
	s = splx(UUIPL);
	if ((bp->b_flags&B_READ) == 0)
		tu_pee(&uu_pcnt[unit]);
	bp->b_actf = NULL;
	if (uutab->b_actf == NULL)
		uutab->b_actf = bp;
	else
		uutab->b_actl->b_actf = bp;
	uutab->b_actl = bp;
	if (uutab->b_active == 0)
		uustart(ui);
	splx(s);
	return;

bad:
	bp->b_flags |= B_ERROR;
	bp->b_error = ENXIO;
	iodone(bp);
	return;
}

/*
 * Start the transfer
 */
uustart(ui)
	register struct uba_device *ui;
{
	register struct buf *bp;
	register struct uu_softc *uuc;
	struct packet *cmd;
	int ctlr = ui->ui_unit, s;

	if ((bp = uitab[ctlr].b_actf) == NULL)
		return;
	s = splx(UUIPL);
	uuc = &uu_softc[ctlr];
	if (uuc->tu_state != TUS_IDLE) {
		uureset(ctlr);
		splx(s);
		return;
	}
	cmd = &uucmd[ctlr];
	uitab[ctlr].b_active++;
	uitab[ctlr].b_errcnt = 0;
	uuc->tu_addr = bp->b_un.b_addr;
	uuc->tu_count = cmd->pk_count = bp->b_bcount;
	cmd->pk_block = bp->b_blkno;
	if (bp->b_flags&B_READ) {
		cmd->pk_op = TUOP_READ;
		cmd->pk_mod = 0;
		uuc->tu_state = TUS_SENDR;
	} else {
		cmd->pk_op = TUOP_WRITE;
		cmd->pk_mod = minor(bp->b_dev)&WRV ? TUMD_WRV : 0;
		uuc->tu_state = TUS_SENDW;
	}
	cmd->pk_unit = UNIT(bp->b_dev)&UMASK;
	cmd->pk_sw = 0;
	cmd->pk_chksum =
	    tuchk(*((short *)cmd), (u_short *)&cmd->pk_op, (int)cmd->pk_mcount);
	uuc->tu_wbptr = (u_char *)cmd;
	uuc->tu_wcnt = sizeof (*cmd);
	uuxintr(ctlr);
	splx(s);
}

/*
 * TU58 receiver interrupt, handles whatever condition the
 * pseudo DMA routine in locore is unable to handle, 
 * or, if UUDMA is undefined, handle all receiver interrupt
 * processing.
 */
uurintr(ctlr)
	int ctlr;
{
	struct uba_device *ui = uudinfo[ctlr];
	register struct uu_softc *uuc = &uu_softc[ctlr];
	register struct uudevice *uuaddr = (struct uudevice *)ui->ui_addr;
	register struct buf *uutab = &uitab[ctlr];
	struct packet *data, *cmd;
	struct buf *bp;
	int c, unit;

	c = uuaddr->rdb;
	data = &uudata[ctlr];
	cmd = &uucmd[ctlr];
#if !defined(UUDMA)
	if (c & UURDB_ERROR)
		uuc->tu_state = TUS_RCVERR;
	else {
		if (uuc->tu_rcnt) {
			*uuc->tu_rbptr++ = c;
			if (--uuc->tu_rcnt)
				return;
		}
	}
#endif

	/*
	 * Switch on the tu_state of the transfer.
	 */
	switch(uuc->tu_state) {

	/*
	 * A data error occured in uudma
	 * (either overrun or break)
	 */
	case TUS_RCVERR:
		if ((c & UURDB_ORUN) == 0)
			printf("uu%d: break received, transfer restarted\n",
			    data->pk_unit);
#ifdef UUDEBUG
		else
			printf("uu%d: data overrun, recovered\n", 
			    data->pk_unit);
#endif
		uuc->tu_serrs++;
		uu_restart(ctlr, ui);	
		break;

	/*
	 * If we get an unexpected "continue",
	 * start all over again...
	 */
	case TUS_INIT2:
		uuc->tu_state = c == TUF_CONT ? TUS_IDLE : TUS_INIT1;
		uuc->tu_flag = 0;
		wakeup((caddr_t)uuc);
		uustart(ui);
		break;

	/*
	 * Only transition from this state
	 * is on a "continue", so if we don't
	 * get it, reset the world.
	 */
	case TUS_WAIT:			/* waiting for continue */
		switch(c) {
		case TUF_CONT:  /* got the expected continue */
			uuc->tu_flag = 0;
			data->pk_flag = TUF_DATA;
			data->pk_mcount = MIN(128, uuc->tu_count);
			data->pk_chksum =
			    tuchk(*((short *)data), (caddr_t)uuc->tu_addr,
				(int)data->pk_mcount);
			uuc->tu_state = TUS_SENDH;
			uuc->tu_wbptr = (u_char *)data;
			uuc->tu_wcnt = 2;
			uuxintr(ctlr);
			break;

		case TUF_CMD:   /* sending us an END packet...error */
			uuc->tu_state = TUS_GET;
			uuc->tu_rbptr = (u_char *)data;
			uuc->tu_rcnt = sizeof (*data) - 1;
			uuc->tu_flag = 1;
			uuaddr->tcs = 0;
			*uuc->tu_rbptr++ = c & UUDB_DMASK;
			break;

		case TUF_INITF:
			uureset(ctlr);
			break;