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📄 ees.p

📁 <B>Digital的Unix操作系统VAX 4.2源码</B>
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(*#@(#)ees.p	4.1	Ultrix	7/17/90 *)(**************************************************************************** *									    * *  Copyright (c) 1984 by						    * *  DIGITAL EQUIPMENT CORPORATION, Maynard, Massachusetts.		    * *  All rights reserved.						    * * 									    * *  This software is furnished under a license and may be used and copied   * *  only in  accordance with  the  terms  of  such  license  and with the   * *  inclusion of the above copyright notice. This software or  any  other   * *  copies thereof may not be provided or otherwise made available to any   * *  other person.  No title to and ownership of  the  software is  hereby   * *  transferred.							    * * 									    * *  The information in this software is  subject to change without notice   * *  and  should  not  be  construed as  a commitment by DIGITAL EQUIPMENT   * *  CORPORATION.							    * * 									    * *  DIGITAL assumes no responsibility for the use  or  reliability of its   * *  software on equipment which is not supplied by DIGITAL.		    * * 									    *$Header: ees.p,v 1.4 84/05/19 11:32:44 powell Exp $ ****************************************************************************)#include "globals.h"type    RegRecord = record	suitable : set of RegState;	regGroup : (RGSINGLE, RGPAIR1, RGPAIR2);	maskbit : integer;	case state : RegState of	    REGDISP : (level : Level; param : boolean; inUse : boolean);	    REGEES : (eesElement : EESElement);    end;    IntRegRec = record case boolean of	true : (int : integer);	false : (reg : Reg);    end;var    regTable : array [Reg] of RegRecord;function ActiveReg{(r : Reg) : boolean};begin    ActiveReg := not (r in [NULLREG,rt0..rt9]);end;function MemTReg{(offset : integer) : Reg};var    ir : IntRegRec;begin    ir.int := ord(rt0) + offset div WORDSIZE;    MemTReg := ir.reg;end;function TRegReg{(r : Reg) : Reg};var    ir : IntRegRec;begin    ir.int := ord(firsttreg) + ord(r) - ord(rt0);    TRegReg := ir.reg;end;procedure ClearAddress{(e:EESElement)};begin    with ees[e] do begin	{ees[e].}addrMemType := ' ';	{ees[e].}addrOffset := 0;	{ees[e].}addrBlock := 0;	{ees[e].}addrLevel := 0;	{ees[e].}indirect := false;    end;end;procedure ClearEES{(e : EESElement)};begin    with ees[e] do begin	{ees[e].}kind := EESDATA;	{ees[e].}dreg := NULLREG;	{ees[e].}breg := NULLREG;	{ees[e].}sreg := NULLREG;	{ees[e].}sunits := 0;	{ees[e].}constInt := 0;	{ees[e].}ptype:=tundefined;	{ees[e].}size:=0;	ClearAddress(e);	{ees[e].}smemoffset:=0;	{ees[e].}smemsize:=0;	{ees[e].}inUse:=false;	{ees[e].}indirect:=false;    end;end;procedure Push{(kind : EESKind)};begin    if top >= EESSTACKSIZE then begin	Error('Push: top > EESSTACKSIZE');    end else begin	top:=top+1;	ClearEES(top);	ees[top].kind := kind;	ees[top].inUse := true;    end;end;procedure Pop{(num:integer)};var    e : EESElement;begin    if (top<num) then begin	Error('Pop: top < num');    end else begin	for e := top downto top-num+1 do begin	    if ees[e].kind = EESDATA then begin		FreeReg(ees[e].dreg);	    end else if ees[e].kind in [EESADDR,EESVAR] then begin		FreeReg(ees[e].sreg);		FreeReg(ees[e].breg);	    end;	    if ees[e].smemsize <> 0 then begin		FreeStack(ees[e].smemoffset,ees[e].smemsize);	    end;	    ClearEES(top);	end;	top := top - num;    end;end;procedure InitEES;var    e : EESElement;begin    for e := NUMTEMPS to EESSTACKSIZE do begin	ClearEES(e);    end;    top := 0;end;procedure InitReg;var    r, rr : Reg;    mask : integer;begin    for r := NULLREG to LASTVREG do begin	regTable[r].suitable := [];	regTable[r].state := REGALLOC;	regTable[r].inUse := false;	regTable[r].regGroup := RGSINGLE;	if r in [r6..r11] then begin	    mask := 32;	    for rr := r6 to r do begin		mask := mask + mask;	    end;	    regTable[r].maskbit := mask;	end else begin	    regTable[r].maskbit := 0;	end;    end;    regTable[RETURNREG].suitable := [REGRETURN];    regTable[RETURNREG].state := REGFREE;    for r := FIRSTREG to LASTREG do begin	regTable[r].suitable := [REGTEMP,REGDISP,REGEES];	regTable[r].state := REGFREE;    end;    for r := FIRSTVREG to LASTVREG do begin	regTable[r].suitable := [REGEES];	regTable[r].state := REGFREE;    end;end;procedure StealReg(stealr, replacer : Reg);begin    if regTable[stealr].state in [REGDISP,REGFREE] then begin	{ don't need to steal it }    end else if regTable[stealr].regGroup <> RGSINGLE then begin	if (regTable[stealr].regGroup <> RGPAIR1)		or (regTable[stealr].regGroup <> RGPAIR2)	then begin	    Error('StealReg: error in reg pairing');	end;	ees[regTable[stealr].eesElement].dreg := replacer;	{ steal reg pair, moving value to virtual reg }	Op('movq'); R(stealr); X; R(replacer); L;	regTable[replacer].state := regTable[stealr].state;	regTable[replacer].eesElement := regTable[stealr].eesElement;	regTable[replacer].regGroup := regTable[stealr].regGroup;	regTable[succ(replacer)].state := regTable[succ(stealr)].state;	regTable[succ(replacer)].eesElement := regTable[succ(stealr)].eesElement;	regTable[succ(replacer)].regGroup := regTable[succ(stealr)].regGroup;	{ free second reg of stolen pair }	regTable[succ(stealr)].state := REGFREE;	regTable[stealr].regGroup := RGSINGLE;	regTable[succ(stealr)].regGroup := RGSINGLE;    end else begin	if ees[regTable[stealr].eesElement].dreg = stealr then begin	    ees[regTable[stealr].eesElement].dreg := replacer;	end else if ees[regTable[stealr].eesElement].breg = stealr	then begin	    ees[regTable[stealr].eesElement].breg := replacer;	end else if ees[regTable[stealr].eesElement].sreg = stealr	then begin	    ees[regTable[stealr].eesElement].sreg := replacer;	end else begin	    Error('StealReg: could not find register usage');	end;	{ steal reg, moving value to virtual reg }	Op('movl'); R(stealr); X; R(replacer); L;	regTable[replacer].state := regTable[stealr].state;	regTable[replacer].eesElement := regTable[stealr].eesElement;    end;end;{ AllocReg:  allocate a register. }{  Make sure it can handle specified type.  Allocate two regs if necessary }{  Assign it to specified stack element }{  NOTE:  All searching must be done from lowest to highest in order to handle }{	register pairs properly }function AllocReg{(state : RegState; e : EESElement; ptype : pcodetype) : Reg};var    r, stealr : Reg;    found, tworegs : boolean;begin    tworegs := ptype = tlongreal;    if state = REGRETURN then begin	{ return reg must be in special place }	if (regTable[RETURNREG].state <> REGFREE) or		(tworegs and (regTable[succ(RETURNREG)].state <> REGFREE))	then begin	    Error('AllocReg: return reg not available');	    r := RETURNREG;	end else begin	    r := RETURNREG;	end;    end else begin	{ look for a reg in normal ones }        r := FIRSTREG;	found := false;	while (r <= lastreg) and not found do begin	    if (regTable[r].state = REGFREE) and		(not tworegs or (regTable[succ(r)].state = REGFREE))	    then begin		found := true;	    end else begin		r := succ(r);	    end;	end;	if not found then begin	    { look for an unused display reg }	    r := FIRSTREG;	    found := false;	    while (r <= lastreg) and not found do begin		if ((regTable[r].state = REGDISP) and not regTable[r].inUse) or			(regTable[r].state = REGFREE)		then begin		    if not tworegs then begin			found := true;		    end else if r = lastreg then begin			{ can't split value between regs and memory }		    end else if (regTable[succ(r)].state = REGFREE) or			((regTable[succ(r)].state = REGDISP) and			    not regTable[succ(r)].inUse)		    then begin			found := true;		    end;		end;		if not found then begin		    r := succ(r);		end;	    end;	end;	if not found then begin	    { didn't find a real reg, allocate a virtual one }	    r := FIRSTVREG;	    found := false;	    while (r <= LASTVREG) and not found do begin		{ always make sure next reg is available, in case we need it }		{   in order to steal the first of a pair }		if (regTable[r].state = REGFREE) and			(regTable[succ(r)].state = REGFREE)		then begin		    found := true;		end else begin		    r := succ(r);		end;	    end;	    if not found then begin		Error('AllocReg: virtual reg not available');	    end else if state in [REGREG, REGDISP] then begin		{ need a real reg, find one to steal }		if tworegs then begin		    Error('AllocReg: tworegs and REGREG');		end;		stealr := FIRSTREG;		found := false;		while (stealr <= lastreg) and not found do begin		    if regTable[stealr].state = REGEES then begin			found := true;		    end else begin			stealr := succ(stealr);		    end;		end;		if not found then begin		    Error('AllocReg: could not steal reg');		end else begin		    StealReg(stealr,r);		    r := stealr;		end;	    end;	end;    end;    regTable[r].state := state;    regTable[r].eesElement := e;    if regTable[r].maskbit <> 0 then begin

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