ms.h

<B>SMSC USB2.0 Flash硬盘驱动源码</B>

/*============================================================================
  ____________________________________________________________________________
                                ______________________________________________
   SSSS  M   M          CCCC          Standard Microsystems Corporation
  S      MM MM   SSSS  C                    Austin Design Center
   SSS   M M M  S      C                 11000 N. Mopac Expressway
      S  M   M   SSS   C                Stonelake Bldg. 6, Suite 500
  SSSS   M   M      S   CCCC                Austin, Texas 78759
                SSSS            ______________________________________________
  ____________________________________________________________________________
  Copyright(C) 1999, Standard Microsystems Corporation
  All Rights Reserved.
  This program code listing is proprietary to SMSC and may not be copied,
  distributed, or used without a license to do so.  Such license may have
  Limited or Restricted Rights. Please refer to the license for further
  clarification.
  ____________________________________________________________________________
  Notice: The program contained in this listing is a proprietary trade
  secret of SMSC, Hauppauge, New York, and is copyrighted
  under the United States Copyright Act of 1976 as an unpublished work,
  pursuant to Section 104 and Section 408 of Title XVII of the United
  States code. Unauthorized copying, adaption, distribution, use, or
  display is prohibited by this law.
  ____________________________________________________________________________
  Use, duplication, or disclosure by the Government is subject to
  restrictions as set forth in subparagraph(c)(1)(ii) of the Rights
  in Technical Data and Computer Software clause at DFARS 52.227-7013.
  Contractor/Manufacturer is Standard Microsystems Corporation,
  80 Arkay Drive, Hauppauge, New York, 1178-8847.
  ____________________________________________________________________________
  ____________________________________________________________________________
  fmcdev.h - USB97210 device specific hardware interface definitions and
             functions that are external to the MCU (ergo external to minimos).
  ____________________________________________________________________________
  comments tbd
  ____________________________________________________________________________
  Revision History
  Date      Who  Comment
  ________  ___  _____________________________________________________________
  09/17/01  cds  initial version
  11/27/01  cds  overrode _lun_enable_mux with fmc code to enable lun data mux
                 without caller needing to know what specific device is at that
                 lun.
  04/02/02  tbh  changed decl of ms_copy_page
  04/17/02  tbh  override dfa_lun_mode_sense
  04/18/02  tbh  removed that override.  superclass method handles it now.
  05/09/02  cds  added msc_rst bit to ms_mode_ctl register
  06/03/02  cds  moved data_fifo macros from .c file to this file so that they
                 could be shared with ms_media.c
  06/05/02  tbh  the _acd_ registers was misnamed _adc_ so i fixed them
  06/20/02  cds  removed obsolete #if k_log_lun_ms < k_max_log_lun guard
  08/13/02  tbh  exported ms_read_status()
  09/25/02  cds  - added support for erase_flash and report_media_geometry to lun vtable
  09/25/02  cds  - added support for erase_flash and report_media_geometry to lun vtable
                 - deleted mode sense dfa
  10/22/02  cds  - defined 210/223 register & bitmask differences...
                   changes are fairly significant, there may be another way to do this
                   (i.e. adding a completely separate "lun" that is ms223, instead of trying
                   to keep these two in sync in the same file, or having "ms" lun and ms_210
                   and ms_223 derivatives)
                 - added following registers for 223:
                    - msc_mode_ctl_1 at XDATA 0x35F2
                    - msc_mode_ctl_2 at XDATA 0x35F3
                    - msc_mode_ctl_3 at XDATA 0x35F8
                    - msc_alt_stat_l at XDATA 0x35F9
                    - msc_alt_stat_h at XDATA 0x35FA
  11/01/02  tbh  made xbuf_rd() visible so ms_media.c can call it.
                 added ms_is_this_blk_in_bad_blk_tbl().
                 added ms_is_this_blk_the_information_block().
  11/03/02  cds  exported g_ms_user_area_start_blk detected when seeking the boot block(s)                 
============================================================================*/
#ifndef __ms_dot_h__
#define __ms_dot_h__

#ifndef __ms_dot_c__
  #define t_ms_register extern unsigned char volatile xdata
  #define at_ms(__addr)
#else
  #define t_ms_register unsigned char volatile xdata
  #define at_ms(__addr)    _at_ 0x35##__addr
#endif
typedef t_xdata_ref t_ms_register_ref;

//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
#define _ms_register_rd(__ref) ((__ref))

//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
#define _ms_register_wr(__ref, __datum) (__ref)=(__datum)

//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
#define _ms_register_setbit(__ref, __bitix) _ms_register_wr((__ref), _ms_register_rd((__ref)) |(1 << (__bitix)))

//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
#define _ms_register_clrbit(__ref, __bitix) _ms_register_wr((__ref), _ms_register_rd((__ref)) & ~(1 << (__bitix)))

//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
#define _ms_register_set_bits(__ref, __bitmsk) _ms_register_wr((__ref), _ms_register_rd((__ref)) |(__bitmsk))

//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
#define _ms_register_clr_bits(__ref, __bitmsk) _ms_register_wr((__ref), _ms_register_rd((__ref)) & ~(__bitmsk))

//------------------------------------------------------------------------------
// memory stick controller (msc) interface registers
t_ms_register ms_tx_db_lsb            at_ms(F4); // rw     tx data buff lsb
t_ms_register ms_tx_db_msb            at_ms(F5); // rw     tx data buff lsb
t_ms_register ms_rx_db_lsb            at_ms(F6); // rw     rx data buff lsb
t_ms_register ms_rx_db_msb            at_ms(F7); // rw     rx data buff lsb

//------------------------------------------------------------------------------
t_ms_register ms_tpc_cmd              at_ms(F0); // rw     tpc command
#define kbm_ms_tpc_cmd_tpc_code_msk   0xF0
#define kbm_ms_tpc_cmd_data_select    0x04
#define kbm_ms_tpc_cmd_bc98_msk       0x03

//------------------------------------------------------------------------------
t_ms_register ms_bc                   at_ms(F1); // rw     byte count7:0

// uses same bits as x_msc_stat


#if defined(k_mcu_97210)

//------------------------------------------------------------------------------
// 210 specific msc register ---------------------------------------------------

//------------------------------------------------------------------------------
t_ms_register ms_fifo_stat            at_ms(F2); // rw     fifo status
#define ms_fifo_stat_r_buf_e          0x08
#define ms_fifo_stat_r_buf_f          0x04
#define ms_fifo_stat_t_buf_e          0x02
#define ms_fifo_stat_t_buf_f          0x01

//------------------------------------------------------------------------------
t_ms_register ms_mode_ctl             at_ms(F3); // rw     mode control
#define kbm_ms_mode_ctl_msc_rst       0x80
#define kbm_ms_mode_ctl_sien          0x20
#define kbm_ms_mode_ctl_daken         0x10
#define kbm_ms_mode_ctl_crc_dis       0x04
#define kbm_ms_mode_ctl_timer_cnt_msk 0x07

//------------------------------------------------------------------------------
t_ms_register ms_acd_cmd              at_ms(F8); // rw     adc command
#define kbm_ms_acd_cmd_tpc_code_msk   0xF0
#define kbm_ms_acd_cmd_bc98_msk       0x03

//------------------------------------------------------------------------------
t_ms_register ms_acd_bc               at_ms(F9); // rw     adc byte count7:0

//------------------------------------------------------------------------------
t_ms_register ms_acd_ctl              at_ms(FA); // rw     adc control
#define kbm_ms_acd_ctl_adc            0x80
#define kbm_ms_acd_ctl_red            0x40

//------------------------------------------------------------------------------
t_ms_register ms_alt_stat             at_ms(FB); // rw     alternate status

// end 210-specific msc registers ----------------------------------------------
//------------------------------------------------------------------------------

#elif defined(k_mcu_97223)
//------------------------------------------------------------------------------
// 223 specific msc register ---------------------------------------------------

//------------------------------------------------------------------------------
t_ms_register msc_mode_ctl_1          at_ms(F2); // rw  MSC Mode Control 1 reg
#define kbm_ms_mode_ctl_dam           0x80       /* new */
#define kbm_ms_mode_ctl_drm           0x40       /* new */
#define kbm_ms_mode_ctl_drqsl         0x20       /* new */
#define kbm_ms_mode_ctl_rei           0x10       /* new */
#define kbm_ms_mode_ctl_bsy_cnt       0x07       /* new */

t_ms_register msc_mode_ctl_2          at_ms(F3); // rw  MSC Mode Control 2 reg
#define kbm_ms_mode_ctl_rst           0x80
#define kbm_ms_mode_ctl_srac          0x40       /* different meaning, but should be interchangeable */
#define kbm_ms_mode_ctl_crc_dis       0x10
#define kbm_ms_mode_ctl_ien           0x04       /* new */
#define kbm_ms_mode_ctl_fclr          0x02       /* new */
#define kbm_ms_mode_ctl_fdir          0x01       /* new */

t_ms_register msc_mode_ctl_3          at_ms(F8); // rw  MSC Mode Control 3 reg
#define kbm_ms_mode_ctl_pro_en        0x02       /* new */
#define kbm_ms_mode_ctl_mult_en       0x01       /* new */

t_ms_register msc_alt_stat_l          at_ms(F9); // rw  MSC alternative stat lsb reg
#define kbm_ms_alt_stat_fifo_e        0x20       /* new */
#define kbm_ms_alt_stat_fifo_f        0x10       /* new */
#define kbm_ms_alt_stat_ced           0x08       /* new */
#define kbm_ms_alt_stat_err           0x04       /* new */
#define kbm_ms_alt_stat_breq          0x02       /* new */
#define kbm_ms_alt_stat_cnk           0x01       /* new */

t_ms_register msc_alt_stat_h          at_ms(FA); // rw  MSC alternative stat msb reg
#define kbm_ms_alt_stat_int           0x20       /* new */
#define kbm_ms_alt_stat_rdy           0x10       /* new */
#define kbm_ms_alt_stat_crc           0x02       /* new */
#define kbm_ms_alt_stat_toe           0x01       /* new */