os_cpu_a.s

来自「嵌入式触摸屏实验」· S 代码 · 共 63 行

;*
;* File: os_cpu_a.s
;*
;*            (c) Copyright ARM Limited 1999.  All rights reserved. 
;*
;*                               ARM Specific code
;*
;*
; 
;	Functions defined in this module:
;
;	void ARMDisableInt(void)	/* disable interrupts when in SVC */
;	void ARMEnableInt(void)		/* enable interrupts when in SVC */
;	void OSCtxSw(void)		/* context switch */
;	void OSStartHighRdy(void)	/* start highest priority task */

NoInt		EQU	0x80

BIT_TIMER0	EQU	(0x1<<13)
BIT_TIMER3	EQU	(0x1<<10)
BIT_TIMER5	EQU	(0x1<<8)
BIT_SIO		EQU	(0x1<<4)
BIT_EINT4567	EQU	(0x1<<21)

I_ISPC		EQU		0x1e00024
INTMSK		EQU		0x1e0000c
EXTINTPND 	EQU     0x1d20054

		AREA    |Assembly$$code|, CODE, READONLY



;::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::
;-------------------------------------------------------
;	uC/OS Porting Core Function : ARMDisableInt
;::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::

	EXPORT	ARMDisableInt

ARMDisableInt
	STMDB	sp!, {r0}
	MRS		r0, CPSR
	ORR		r0, r0, #NoInt
	MSR		CPSR_cxsf, r0
	LDMIA	sp!, {r0}
	MOV pc, lr

;::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::
;-------------------------------------------------------
;	uC/OS Porting Core Function : ARMEnableInt
;::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::

	EXPORT	ARMEnableInt

ARMEnableInt
	STMDB sp!, {r0}
	MRS r0, CPSR
	BIC r0, r0, #NoInt
	MSR CPSR_cxsf, r0
	LDMIA sp!, {r0}
	MOV pc, lr

    	END