t1.asm

范例程序 SONiX

chip	sn8p26l38
//{{SONIX_CODE_OPTION
	.Code_Option	LVD		LVD_L		; 1.8V Reset
	.Code_Option	Reset_Pin	P02
	.Code_Option	Watch_Dog	Disable
	.Code_Option	High_Clk	4M_X'tal	; Crystal/Resonator: 2Mhz~8Mhz
	.Code_Option	Fcpu		Fosc/4
	.Code_Option	Security	Disable
//}}SONIX_CODE_OPTION

.data
	acc_buf		ds	1
	pflag_buf	ds	1
	T1_buf		ds	1

.code

	org	00h
	jmp	main
	org	08h
	jmp	isr	

	org	10h
//============================================================================
//	timer T1 --> internal clock and auto re-load
//============================================================================

main:
	
	mov	a,#00h
	b0mov	T1_buf,a

	b0bclr	ft1enb					
	mov	a,#20h		//Fcpu/64	
	b0mov	t1m,a			
											
	mov	a,#64h		//10ms	interrupt Once		
	b0mov	t1cl,a		//Write T1CL data into T1CL buffer first.
	mov	a,#064h
	b0mov	t1ch,a 		//Write T1CH data and T1CH, T1CL are imported to T1C
				//16-bit buffer	
								
	b0bset	ft1enb		// Enable Tc0 timer
	b0bset	ft1ien  	// Enable Tc0 interrupt
	b0bclr	ft1irq		// Clean Tc0 interrupt request flag
	b0bset	fgie		// all interrupt operation				
//===========================================================================
//
//	User 	code
//
//=========================================================================== 									
	jmp	main
	
//To set 10ms interval time for T1 interrupt. High clock is external 4MHz. Fcpu=Fosc/4.
// Select T1RATE=010 (Fcpu/64).
// 
//	T1C initial value
//	 = 65536 - (T1 interrupt interval time * input clock) 
//	 = 65536 - (10ms * 4MHz / 4 / 64) 
//	 = 65536 - (10-2 * 4 * 106 / 4 / 64) 
//	 = 65380 
//	 = FF64H 	;T1CH=0xFF, T1CL=0x64
//---------------|--------------|-------------------------------------------|
//   	T1RATE	 |   T1CLOCK    |   High speed mode (Fcpu = 4MHz / 4)       | 
//---------------|--------------|----------------------|--------------------|
//     		 |       	|Max overflow interval | One step = max/256 |
//---------------|--------------|----------------------|--------------------|
//       000     |    Fcpu/256	|       16.777 s       |  	256us       | 
//	 001     |    Fcpu/128	|       8.388 s        | 	128us 	    | 
//	 010     |    Fcpu/64	|   	4.194 s        |  	64us        | 
//	 011     |    Fcpu/32	|   	2.097 s        |  	32us        | 
//	 100     |    Fcpu/16	|   	1.048 s        |  	16us        | 
//	 101     |    Fcpu/8	|   	524.288ms      |  	8us         | 
//	 110     |    Fcpu/4	|   	262.144 ms     |  	4us         | 
//	 111     |    Fcpu/2	|   	131.072 ms     |  	2us         | 
//---------------|--------------|----------------------|--------------------|

isr:

	mov	acc_buf,a			// Push ACC to buffer
	mov	a,pflag
	b0mov	pflag_buf,a			// Push PFLAG to buffer
isr_adc:
	b0bts1	ft1ien				// Check t1ien
	jmp	isr90				
	b0bts1	ft1irq				// Check t1irp
	jmp	isr90			
	b0bclr	ft1irq

	mov	a,#64h				//10ms	interrupt Once 					
	b0mov	t1cl,a				//Write T1CL data into T1CL buffer first.
	mov	a,#0ffh
	b0mov	t1ch,a				//Write T1CH data and T1CH, T1CL are imported to T1C
						//16-bit buffer	
	mov	a,T1_buf
	add	a,#01h				// 10ms add one time 
	b0mov	T1_buf,a
	
isr90:
	mov	a,pflag_buf
	b0mov	pflag,a				// Pop pflag_buf to pflag
	mov	a,acc_buf			// Pop acc_buf to acc
	reti