📄 s3c4510b.s
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; 0x4=5Cycle, 0x5=6Cycle
; 0x6=7Cycle, 0x7=Reserved
rROMCON1 EQU ROMEndPtr1+ROMBasePtr1+rTacc1+rTpa1+PMC1
;-------------------------------------------------------------
;/* -> ROMCON2 : ROM Bank2 Control register */
;-------------------------------------------------------------
ROMBasePtr2 EQU 0x040:SHL:10 ;=0x0400000
ROMEndPtr2 EQU 0x060:SHL:20 ;=0x0600000
PMC2 EQU 0x0 ; 0x0=Normal ROM, 0x1=4Word Page
; 0x2=8Word Page, 0x3=16Word Page
rTpa2 EQU (0x0:SHL:2) ; 0x0=5Cycle, 0x1=2Cycle
; 0x2=3Cycle, 0x3=4Cycle
rTacc2 EQU (0x4:SHL:4) ; 0x0=Disable, 0x1=2Cycle
; 0x2=3Cycle, 0x3=4Cycle
; 0x4=5Cycle, 0x5=6Cycle
; 0x6=7Cycle, 0x7=Reserved
rROMCON2 EQU 0x60
;rROMCON2 EQU ROMEndPtr2+ROMBasePtr2+rTacc2+rTpa2+PMC2
;-------------------------------------------------------------
;/* -> ROMCON3 : ROM Bank3 Control register */
;-------------------------------------------------------------
ROMBasePtr3 EQU 0x060:SHL:10 ;=0x0600000
ROMEndPtr3 EQU 0x080:SHL:20 ;=0x0800000
PMC3 EQU 0x0 ; 0x0=Normal ROM, 0x1=4Word Page
; 0x2=8Word Page, 0x3=16Word Page
rTpa3 EQU (0x0:SHL:2) ; 0x0=5Cycle, 0x1=2Cycle
; 0x2=3Cycle, 0x3=4Cycle
rTacc3 EQU (0x2:SHL:4) ; 0x0=Disable, 0x1=2Cycle
; 0x2=3Cycle, 0x3=4Cycle
; 0x4=5Cycle, 0x5=6Cycle
; 0x6=7Cycle, 0x7=Reserved
rROMCON3 EQU 0x60
;rROMCON3 EQU ROMEndPtr3+ROMBasePtr3+rTacc3+rTpa3+PMC3
;-------------------------------------------------------------
;/* -> ROMCON4 : ROM Bank4 Control register */
;-------------------------------------------------------------
ROMBasePtr4 EQU 0x080:SHL:10 ;=0x0800000
ROMEndPtr4 EQU 0x0A0:SHL:20 ;=0x0A00000
PMC4 EQU 0x0 ; 0x0=Normal ROM, 0x1=4Word Page
; 0x2=8Word Page, 0x3=16Word Page
rTpa4 EQU (0x0:SHL:2) ; 0x0=5Cycle, 0x1=2Cycle
; 0x2=3Cycle, 0x3=4Cycle
rTacc4 EQU (0x4:SHL:4) ; 0x0=Disable, 0x1=2Cycle
; 0x2=3Cycle, 0x3=4Cycle
; 0x4=5Cycle, 0x5=6Cycle
; 0x6=7Cycle, 0x7=Reserved
rROMCON4 EQU 0x60
;rROMCON4 EQU ROMEndPtr4+ROMBasePtr4+rTacc4+rTpa4+PMC4
;-------------------------------------------------------------
;/* -> ROMCON5 : ROM Bank5 Control register */
;-------------------------------------------------------------
ROMBasePtr5 EQU 0x0A0:SHL:10 ;=0x0A00000
ROMEndPtr5 EQU 0x0C0:SHL:20 ;=0x0C00000
PMC5 EQU 0x0 ; 0x0=Normal ROM, 0x1=4Word Page
; 0x2=8Word Page, 0x3=16Word Page
rTpa5 EQU (0x0:SHL:2) ; 0x0=5Cycle, 0x1=2Cycle
; 0x2=3Cycle, 0x3=4Cycle
rTacc5 EQU (0x4:SHL:4) ; 0x0=Disable, 0x1=2Cycle
; 0x2=3Cycle, 0x3=4Cycle
; 0x4=5Cycle, 0x5=6Cycle
; 0x6=7Cycle, 0x7=Reserved
rROMCON5 EQU 0x60
;rROMCON5 EQU ROMEndPtr5+ROMBasePtr5+rTacc5+rTpa5+PMC5
;-------------------------------------------------------------
;/* -> DRAMCON0 : RAM Bank0 control register */
;-------------------------------------------------------------
EDO_Mode0 EQU 1 ;(EDO)0=Normal, 1=EDO DRAM
CasPrechargeTime0 EQU 0 ;(Tcp)0=1cycle,1=2cycle
CasStrobeTime0 EQU 1 ;(Tcs)0=1cycle ~ 3=4cycle
DRAMCON0Reserved EQU 1 ; Must be set to 1
RAS2CASDelay0 EQU 0 ;(Trc)0=1cycle,1=2cycle
RASPrechargeTime0 EQU 2 ;(Trp)0=1cycle ~ 3=4clcyle
DRAMBasePtr0 EQU 0x10:SHL:10 ;=0x00100000 1M
DRAMEndPtr0 EQU 0x110:SHL:20 ;=0x01100000 17M
NoColumnAddr0 EQU 2 ;0=8bit,1=9bit,2=10bit,3=11bits
;-------------------------------------------------------------
Tcs0 EQU CasStrobeTime0:SHL:1
Tcp0 EQU CasPrechargeTime0:SHL:3
dumy0 EQU DRAMCON0Reserved:SHL:4 ; dummy cycle
Trc0 EQU RAS2CASDelay0:SHL:7
Trp0 EQU RASPrechargeTime0:SHL:8
CAN0 EQU NoColumnAddr0:SHL:30
;
rDRAMCON0 EQU CAN0+DRAMEndPtr0+DRAMBasePtr0+Trp0+Trc0+Tcp0+Tcs0+dumy0+EDO_Mode0
;----------------------------------------------------------------------------------
SRAS2CASDelay0 EQU 1 ;(Trc)0=1cycle,1=2cycle
SRASPrechargeTime0 EQU 3 ;(Trp)0=1cycle ~ 3=4clcyle
SNoColumnAddr0 EQU 0 ;0=8bit,1=9bit,2=10bit,3=11bits
SCAN0 EQU SNoColumnAddr0:SHL:30
STrc0 EQU SRAS2CASDelay0:SHL:7
STrp0 EQU SRASPrechargeTime0:SHL:8
;
rSDRAMCON0 EQU SCAN0+DRAMEndPtr0+DRAMBasePtr0+STrp0+STrc0;+dumy0
;/* -> DRAMCON0 : RAM Bank0 control register remap */
;-------------------------------------------------------------
DRAMBasePtr0_S EQU 0x000:SHL:10 ;=0x1000000 0M
DRAMEndPtr0_S EQU 0x100:SHL:20 ;=0x2000000 16M
rSDRAMCON0_S EQU SCAN0+DRAMEndPtr0_S+DRAMBasePtr0_S+STrp0+STrc0
;/* -> DRAMCON1 : RAM Bank1 control register */
;-------------------------------------------------------------
EDO_Mode1 EQU 1 ;(EDO)0=Normal, 1=EDO DRAM
CasPrechargeTime1 EQU 0 ;(Tcp)0=1cycle,1=2cycle
CasStrobeTime1 EQU 1 ;(Tcs)0=1cycle ~ 3=4cycle
DRAMCON1Reserved EQU 0 ; Must be set to 1
RAS2CASDelay1 EQU 0 ;(Trc)0=1cycle,1=2cycle
RASPrechargeTime1 EQU 0 ;(Trp)0=1cycle ~ 3=4clcyle
DRAMBasePtr1 EQU 0x140:SHL:10 ;=0x14000000
DRAMEndPtr1 EQU 0x180:SHL:20 ;=0x18000000
NoColumnAddr1 EQU 2 ;0=8bit,1=9bit,2=10bit,3=11bits
;-------------------------------------------------------------
Tcs1 EQU CasStrobeTime1:SHL:1
Tcp1 EQU CasPrechargeTime1:SHL:3
dumy1 EQU DRAMCON1Reserved:SHL:4 ; dummy cycle
Trc1 EQU RAS2CASDelay1:SHL:7
Trp1 EQU RASPrechargeTime1:SHL:8
CAN1 EQU NoColumnAddr1:SHL:30
;
rDRAMCON1 EQU CAN1+DRAMEndPtr1+DRAMBasePtr1+Trp1+Trc1+Tcp1+Tcs1+dumy1+EDO_Mode1
;----------------------------------------------------------------------------------
SRAS2CASDelay1 EQU 1 ;(Trc)0=1cycle,1=2cycle
SRASPrechargeTime1 EQU 1 ;(Trp)0=1cycle ~ 3=4clcyle
SNoColumnAddr1 EQU 0 ;0=8bit,1=9bit,2=10bit,3=11bits
SCAN1 EQU SNoColumnAddr1:SHL:30
STrc1 EQU SRAS2CASDelay1:SHL:7
STrp1 EQU SRASPrechargeTime1:SHL:8
;
rSDRAMCON1 EQU 0x00
;rSDRAMCON1 EQU SCAN1+DRAMEndPtr1+DRAMBasePtr1+STrp1+STrc1
;-------------------------------------------------------------
;/* -> DRAMCON2 : RAM Bank2 control register */
;-------------------------------------------------------------
EDO_Mode2 EQU 0 ;(EDO)0=Normal, 1=EDO DRAM
CasPrechargeTime2 EQU 0 ;(Tcp)0=1cycle,1=2cycle
CasStrobeTime2 EQU 1 ;(Tcs)0=1cycle ~ 3=4cycle
DRAMCON2Reserved EQU 1 ; Must be set to 1
RAS2CASDelay2 EQU 0 ;(Trc)0=1cycle,1=2cycle
RASPrechargeTime2 EQU 0 ;(Trp)0=1cycle ~ 3=4clcyle
DRAMBasePtr2 EQU 0x180:SHL:10 ;=0x14000000
DRAMEndPtr2 EQU 0x1C0:SHL:20 ;=0x18000000
NoColumnAddr2 EQU 2 ;0=8bit,1=9bit,2=10bit,3=11bits
;-------------------------------------------------------------
Tcs2 EQU CasStrobeTime2:SHL:1
Tcp2 EQU CasPrechargeTime2:SHL:3
dumy2 EQU DRAMCON2Reserved:SHL:4 ; dummy cycle
Trc2 EQU RAS2CASDelay2:SHL:7
Trp2 EQU RASPrechargeTime2:SHL:8
CAN2 EQU NoColumnAddr2:SHL:30
;
rDRAMCON2 EQU CAN2+DRAMEndPtr2+DRAMBasePtr2+Trp2+Trc2+Tcp2+Tcs2+dumy2+EDO_Mode2
;--------------------------
SRAS2CASDelay2 EQU 1 ;(Trc)0=1cycle,1=2cycle
SRASPrechargeTime2 EQU 1 ;(Trp)0=1cycle ~ 3=4clcyle
SNoColumnAddr2 EQU 0 ;0=8bit,1=9bit,2=10bit,3=11bits
SCAN2 EQU SNoColumnAddr2:SHL:30
STrc2 EQU SRAS2CASDelay2:SHL:7
STrp2 EQU SRASPrechargeTime2:SHL:8
;
rSDRAMCON2 EQU 0x00
;rSDRAMCON2 EQU SCAN2+DRAMEndPtr2+DRAMBasePtr2+STrp2+STrc2
;-------------------------------------------------------------
;/* -> DRAMCON3 : RAM Bank3 control register */
;-------------------------------------------------------------
EDO_Mode3 EQU 0 ;(EDO)0=Normal, 1=EDO DRAM
CasPrechargeTime3 EQU 0 ;(Tcp)0=1cycle,1=2cycle
CasStrobeTime3 EQU 1 ;(Tcs)0=1cycle ~ 3=4cycle
DRAMCON3Reserved EQU 1 ; Must be set to 1
RAS2CASDelay3 EQU 0 ;(Trc)0=1cycle,1=2cycle
RASPrechargeTime3 EQU 0 ;(Trp)0=1cycle ~ 3=4clcyle
DRAMBasePtr3 EQU 0x1C0:SHL:10 ;=0x14000000
DRAMEndPtr3 EQU 0x200:SHL:20 ;=0x18000000
NoColumnAddr3 EQU 2 ;0=8bit,1=9bit,2=10bit,3=11bits
;-------------------------------------------------------------
Tcs3 EQU CasStrobeTime3:SHL:1
Tcp3 EQU CasPrechargeTime3:SHL:3
dumy3 EQU DRAMCON3Reserved:SHL:4 ; dummy cycle
Trc3 EQU RAS2CASDelay3:SHL:7
Trp3 EQU RASPrechargeTime3:SHL:8
CAN3 EQU NoColumnAddr3:SHL:30
;
rDRAMCON3 EQU CAN3+DRAMEndPtr3+DRAMBasePtr3+Trp3+Trc3+Tcp3+Tcs3+dumy3+EDO_Mode3
;--------------------------
SRAS2CASDelay3 EQU 1 ;(Trc)0=1cycle,1=2cycle
SRASPrechargeTime3 EQU 1 ;(Trp)0=1cycle ~ 3=4clcyle
SNoColumnAddr3 EQU 0 ;0=8bit,1=9bit,2=10bit,3=11bits
SCAN3 EQU SNoColumnAddr3:SHL:30
STrc3 EQU SRAS2CASDelay3:SHL:7
STrp3 EQU SRASPrechargeTime3:SHL:8
;
rSDRAMCON3 EQU 0x00
;rSDRAMCON3 EQU SCAN3+DRAMEndPtr3+DRAMBasePtr3+STrp3+STrc3
;-------------------------------------------------------------
;/* -> REFEXTCON : External I/O & Memory Refresh cycle Control Register */
;-------------------------------------------------------------
RefCycle EQU 16 ;Unit [us], 1k refresh 16ms
;RefCycle EQU 8 ;Unit [us], 1k refresh 16ms
CASSetupTime EQU 0 ;0=1cycle, 1=2cycle
CASHoldTime EQU 0 ;0=1cycle, 1=2cycle, 2=3cycle,
;3=4cycle, 4=5cycle,
RefCycleValue EQU ((2048+1-(RefCycle*fMCLK)):SHL:21)
Tcsr EQU (CASSetupTime:SHL:20) ; 1cycle
Tcs EQU (CASHoldTime:SHL:17)
ExtIOBase EQU 0x18360 ; Refresh enable, VSF=1
;
rREFEXTCON EQU RefCycleValue+Tcsr+Tcs+ExtIOBase
;-------------------------------------------------------------
;SRefCycle EQU 16 ;Unit [us], 4k refresh 64ms
SRefCycle EQU 8 ;Unit [us], 4k refresh 64ms
ROWcycleTime EQU 3 ;0=1cycle, 1=2cycle, 2=3cycle,
;3=4cycle, 4=5cycle,
SRefCycleValue EQU ((2048+1-(SRefCycle*fMCLK)):SHL:21)
STrc EQU (ROWcycleTime:SHL:17)
rSREFEXTCON EQU SRefCycleValue+STrc+ExtIOBase
;-------------------------------------------------------------
;/***************************************************************/
END
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