📄 main.lst
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214 CSN = 1; // CSN high again
215
216 return(status); // return nRF24L01 status byte
217 }
218 BYTE SPI_Read(BYTE reg)
219 {
220 BYTE reg_val;
221
222 CSN = 0; // CSN low, initialize SPI communication...
223 SPI_RW(reg); // Select register to read from..
224 reg_val = SPI_RW(0); // ..then read registervalue
225 CSN = 1; // CSN high, terminate SPI communication
226
227 return(reg_val); // return register value
228 }
229
230
231
232 uchar SPI_Read_Buf(BYTE reg, BYTE *pBuf, BYTE bytes)
233 {
234 uchar status,byte_ctr;
235
236 CSN = 0; // Set CSN low, init SPI tranaction
237 status = SPI_RW(reg); // Select register to write to and read status byte
238
239 for(byte_ctr=0;byte_ctr<bytes;byte_ctr++)
240 pBuf[byte_ctr] = SPI_RW(0); // Perform SPI_RW to read byte from nRF24L01
C51 COMPILER V7.50 MAIN 05/25/2010 11:46:57 PAGE 5
241
242 CSN = 1; // Set CSN high again
243
244 return(status); // return nRF24L01 status byte
245 }
246 uchar SPI_Write_Buf(BYTE reg, BYTE *pBuf, BYTE bytes)
247 {
248 uchar status,byte_ctr;
249
250 CSN = 0; // Set CSN low, init SPI tranaction
251 status = SPI_RW(reg); // Select register to write to and read status byte
252 for(byte_ctr=0; byte_ctr<bytes; byte_ctr++) // then write all byte in buffer(*pBuf)
253 SPI_RW(*pBuf++);
254 CSN = 1; // Set CSN high again
255 return(status); // return nRF24L01 status byte
256 }
257 void Set_RX()
258 {
259 CE=0;
260 SPI_RW_Reg(WRITE_REG + CONFIG,0x0f);
261 SPI_RW_Reg(WRITE_REG + RX_PW_P0,TX_PLOAD_WIDTH);
262 CE=1;
263 delays(130);
264 }
265 void Set_TX()
266 {
267 CE=0;
268
269 SPI_Write_Buf(WRITE_REG + RX_ADDR_P0,TX_ADDRESS,TX_ADR_WIDTH);
270 SPI_Write_Buf(WR_TX_PLOAD,tx_buf,TX_PLOAD_WIDTH);
271
272 SPI_RW_Reg(WRITE_REG + CONFIG,0x0e);
273
274 CE=1;
275 delays(130);
276 }
277 void init_24L01()
278 { CE=0;
279
280 SPI_Write_Buf(WRITE_REG + TX_ADDR, TX_ADDRESS, TX_ADR_WIDTH); // Writes TX_Address to nRF24L01
281 SPI_Write_Buf(WRITE_REG + RX_ADDR_P0,TX_ADDRESS, TX_ADR_WIDTH);
282
283 SPI_RW_Reg(WRITE_REG + EN_AA, 0x01); // Enable Auto.Ack:Pipe0
284 SPI_RW_Reg(WRITE_REG + EN_RXADDR, 0x01); // Enable Pipe0
285 SPI_RW_Reg(WRITE_REG + SETUP_RETR, 0x1a); // 500us + 86us, 10 retrans...
286 SPI_RW_Reg(WRITE_REG + RF_CH,100); // Select RF channel 40
287 SPI_RW_Reg(WRITE_REG + RF_SETUP, 0x0f); // TX_PWR:0dBm, Datarate:2Mbps, LNA:HCURR
288 SPI_RW_Reg(WRITE_REG + CONFIG, 0x0e); // Set PWR_UP bit, enable CRC(2 bytes) & Prim:TX. MAX_RT & TX_
-DS enabled..
289 CE=1;
290 }
291 /*void RX_Mode(void)
292 {
293 CE=0;
294 SPI_Write_Buf(WRITE_REG + RX_ADDR_P0, TX_ADDRESS, TX_ADR_WIDTH); // Use the same address on the RX devi
-ce as the TX device
295
296 SPI_RW_Reg(WRITE_REG + EN_AA, 0x01); // Enable Auto.Ack:Pipe0
297 SPI_RW_Reg(WRITE_REG + EN_RXADDR, 0x01); // Enable Pipe0
298 SPI_RW_Reg(WRITE_REG + RF_CH, 40); // Select RF channel 40
299 SPI_RW_Reg(WRITE_REG + RX_PW_P0, TX_PLOAD_WIDTH); // Select same RX payload width as TX Payload width
300 SPI_RW_Reg(WRITE_REG + RF_SETUP, 0x0f); // TX_PWR:0dBm, Datarate:2Mbps, LNA:HCURR
C51 COMPILER V7.50 MAIN 05/25/2010 11:46:57 PAGE 6
301 SPI_RW_Reg(WRITE_REG + CONFIG, 0x0f); // Set PWR_UP bit, enable CRC(2 bytes) & Prim:RX. RX_DR enabl
-ed..
302
303 CE = 1; // Set CE pin high to enable RX device
304 delay(130);
305 // This device is now ready to receive one packet of 16 bytes payload from a TX device sending to addre
-ss
306 // '3443101001', with auto acknowledgment, retransmit count of 10, RF channel 40 and datarate = 2Mbps.
307
308 }
309 void TX_Mode(void)
310 {
311 CE=0;
312 // RX_Addr0 same as TX_Adr for Auto.Ack
313 SPI_Write_Buf(WR_TX_PLOAD, tx_buf, TX_PLOAD_WIDTH); // Writes data to TX payload
314
315 SPI_RW_Reg(WRITE_REG + EN_AA, 0x01); // Enable Auto.Ack:Pipe0
316 SPI_RW_Reg(WRITE_REG + EN_RXADDR, 0x01); // Enable Pipe0
317
318 SPI_RW_Reg(WRITE_REG + RF_CH,40); // Select RF channel 40
319 SPI_RW_Reg(WRITE_REG + RF_SETUP, 0x0f); // TX_PWR:0dBm, Datarate:2Mbps, LNA:HCURR
320 SPI_RW_Reg(WRITE_REG + SETUP_RETR, 0x1a); // 500us + 86us, 10 retrans...
321 SPI_RW_Reg(WRITE_REG + CONFIG, 0x0e); // Set PWR_UP bit, enable CRC(2 bytes) & Prim:TX. MAX_RT & TX
-_DS enabled..
322 CE=1;
323 delays(130);
324
325 */
326
327 /*Got a baby mistake,false key set if key equal 1 enter to function -_-! */
328 void led_shake()
329 {
330 1 led=0;
331 1 delays(500);
332 1 led=1;
333 1 delays(500);
334 1 } //实现按键循环，不实现连续按键组合
335 /*uchar judge_BT(uchar t)
336 {
337 uchar *a;
338 uchar *b;
339 uchar *c;
340
341 a=Original_ADDRESS;
342 b=OnePress_ADDRESS;
343 c=TX_ADDRESS;
344 if(t)
345 {
346 *a=*b;
347 tf=1;
348 }
349 if(t==2)
350 {
351 t=0;
352 *a=*c;
353 tf=1;
354 }
355 if(tf)
356 {
357 tf=0;
358 Set_TX();
359 }
C51 COMPILER V7.50 MAIN 05/25/2010 11:46:57 PAGE 7
360 return (t);
361 } */
362 void CheckButtons()
363 {
364 1 if(key==0)
365 1 {
366 2 delays(100);
367 2 if(key==0)
368 2 {
369 3 led_shake();
370 3 tf=1;
371 3 }
372 2 }
373 1 if(tf)
374 1 {
375 2 tf=0;
376 2 Set_TX();
377 2 }
378 1 /* uchar t;
379 1 uchar *a;
380 1 uchar *b;
381 1 uchar *c;
382 1
383 1 a=Original_ADDRESS;
384 1 b=OnePress_ADDRESS;
385 1 c=TX_ADDRESS;
386 1 if(key==0)
387 1 {
388 1 delays(100);
389 1 if(key==0)
390 1 {
391 1 led_shake();
392 1 t++;
393 1 }
394 1 }
395 1 if(t==1)
396 1 {
397 1 *a=*b;
398 1 tf=1;
399 1 }
400 1 if(t==2)
401 1 {
402 1 t=0;
403 1 *a=*c;
404 1 tf=1;
405 1 } */
406 1 if(tf)
407 1 {
408 2 tf=0;
409 2 Set_TX();
410 2 }
411 1 //judge_BT(t);
412 1
413 1 }
414
415 /*Init HardWare SPI*/
416 void Init_SPI(void)
417 {
418 1 SPI0CFG = 0x40;
419 1 SPI0CN = 0x01; //(This Register can control SCK Pin High Or Low??The function of the pin is Enable/disa
-ble SPI..why add by lsy)
420 1
C51 COMPILER V7.50 MAIN 05/25/2010 11:46:57 PAGE 8
421 1 SPI0CKR = 0x01;
422 1 }
423 void init_mcu(void)
424 {
425 1 // unsigned int i;
426 1 P0MDIN = 0xff; // 01100010
427 1 P0MDOUT = 0x9d; //0:open-drain, 1:push pull (important Setting,If The port ain't t
-he open-drain Mode,It won't be receive any data from register)add by lsy
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