sopc.ptf

一个测试端口测试程序

               width = "32";
            }
            PORT read_n
            {
               direction = "input";
               is_shared = "1";
               type = "read_n";
               width = "1";
            }
            PORT select0_n
            {
               direction = "input";
               is_shared = "0";
               type = "chipselect_n";
               width = "1";
            }
            PORT select1_n
            {
               direction = "input";
               is_shared = "0";
               type = "chipselect_n";
               width = "1";
            }
            PORT write_n
            {
               direction = "input";
               is_shared = "0";
               type = "write_n";
               width = "1";
            }
         }
         SYSTEM_BUILDER_INFO 
         {
            Bus_Type = "avalon_tristate";
            Is_Memory_Device = "1";
            Address_Alignment = "dynamic";
            Data_Width = "32";
            Address_Width = "16";
            Has_IRQ = "0";
            IRQ_Number = "N/A";
            Read_Wait_States = "0";
            Write_Wait_States = "0";
            Hold_Time = "half_clock";
            Base_Address = "0x00040000";
            Address_Span = "262144";
            MASTERED_BY tri_state_bridge_0/tristate_master
            {
               priority = "1";
            }
         }
      }
      SYSTEM_BUILDER_INFO 
      {
         Is_Enabled = "1";
         Instantiate_In_System_Module = "0";
         Make_Memory_Model = "1";
         View 
         {
            Is_Collapsed = "1";
            MESSAGES 
            {
            }
         }
      }
   }
   MODULE tri_state_bridge_0
   {
      class = "altera_avalon_tri_state_bridge";
      class_version = "2.0";
      SLAVE avalon_slave
      {
         SYSTEM_BUILDER_INFO 
         {
            Bus_Type = "avalon";
            Bridges_To = "tristate_master";
            Base_Address = "N/A";
            Has_IRQ = "0";
            IRQ = "N/A";
            Register_Outgoing_Signals = "1";
            Register_Incoming_Signals = "1";
            MASTERED_BY nios32_256/instruction_master
            {
               priority = "1";
            }
            MASTERED_BY nios32_256/data_master
            {
               priority = "1";
            }
         }
      }
      MASTER tristate_master
      {
         SYSTEM_BUILDER_INFO 
         {
            Bus_Type = "avalon_tristate";
            Bridges_To = "avalon_slave";
         }
      }
      SYSTEM_BUILDER_INFO 
      {
         Instantiate_In_System_Module = "1";
         Is_Enabled = "1";
         Is_Bridge = "1";
         View 
         {
            Is_Collapsed = "1";
            MESSAGES 
            {
            }
         }
      }
   }
   MODULE timer_for_test
   {
      class = "altera_avalon_timer";
      class_version = "2.0";
      SLAVE s1
      {
         SYSTEM_BUILDER_INFO 
         {
            Bus_Type = "avalon";
            Is_Printable_Device = "0";
            Address_Alignment = "native";
            Address_Width = "3";
            Data_Width = "16";
            Has_IRQ = "1";
            Read_Wait_States = "1";
            Write_Wait_States = "0";
            IRQ_Number = "20";
            Base_Address = "0x00000440";
            MASTERED_BY nios32_256/data_master
            {
               priority = "1";
            }
         }
         PORT_WIRING 
         {
            PORT address
            {
               direction = "input";
               type = "address";
               width = "3";
            }
            PORT chipselect
            {
               direction = "input";
               type = "chipselect";
               width = "1";
            }
            PORT clk
            {
               direction = "input";
               type = "clk";
               width = "1";
            }
            PORT irq
            {
               direction = "output";
               type = "irq";
               width = "1";
            }
            PORT readdata
            {
               direction = "output";
               type = "readdata";
               width = "16";
            }
            PORT reset_n
            {
               direction = "input";
               type = "reset_n";
               width = "1";
            }
            PORT write_n
            {
               direction = "input";
               type = "write_n";
               width = "1";
            }
            PORT writedata
            {
               direction = "input";
               type = "writedata";
               width = "16";
            }
         }
      }
      SYSTEM_BUILDER_INFO 
      {
         Instantiate_In_System_Module = "1";
         Is_Enabled = "1";
         View 
         {
            Settings_Summary = "Timer with 1 msec timeout period.";
            Is_Collapsed = "1";
            MESSAGES 
            {
            }
         }
      }
      WIZARD_SCRIPT_ARGUMENTS 
      {
         always_run = "0";
         fixed_period = "0";
         snapshot = "1";
         period = "1";
         period_units = "msec";
         reset_output = "0";
         timeout_pulse_output = "0";
         mult = "0.001";
      }
      HDL_INFO 
      {
         Simulation_HDL_Files = "";
         Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/timer_for_test.vhd";
      }
      PORT_WIRING 
      {
      }
   }
   MODULE uart_OSView
   {
      class = "altera_avalon_uart";
      class_version = "2.0";
      SLAVE s1
      {
         SYSTEM_BUILDER_INFO 
         {
            Bus_Type = "avalon";
            Is_Printable_Device = "1";
            Address_Alignment = "native";
            Address_Width = "3";
            Data_Width = "16";
            Has_IRQ = "1";
            Read_Wait_States = "1";
            Write_Wait_States = "1";
            IRQ_Number = "18";
            MASTERED_BY nios32_256/data_master
            {
               priority = "1";
            }
            Base_Address = "0x00000460";
         }
         PORT_WIRING 
         {
            PORT address
            {
               direction = "input";
               type = "address";
               width = "3";
            }
            PORT begintransfer
            {
               direction = "input";
               type = "begintransfer";
               width = "1";
            }
            PORT chipselect
            {
               direction = "input";
               type = "chipselect";
               width = "1";
            }
            PORT clk
            {
               direction = "input";
               type = "clk";
               width = "1";
            }
            PORT dataavailable
            {
               direction = "output";
               type = "dataavailable";
               width = "1";
            }
            PORT irq
            {
               direction = "output";
               type = "irq";
               width = "1";
            }
            PORT read_n
            {
               direction = "input";
               type = "read_n";
               width = "1";
            }
            PORT readdata
            {
               direction = "output";
               type = "readdata";
               width = "16";
            }
            PORT readyfordata
            {
               direction = "output";
               type = "readyfordata";
               width = "1";
            }
            PORT reset_n
            {
               direction = "input";
               type = "reset_n";
               width = "1";
            }
            PORT write_n
            {
               direction = "input";
               type = "write_n";
               width = "1";
            }
            PORT writedata
            {
               direction = "input";
               type = "writedata";
               width = "16";
            }
         }
      }
      SYSTEM_BUILDER_INFO 
      {
         Instantiate_In_System_Module = "1";
         Is_Enabled = "1";
         View 
         {
            Settings_Summary = "8-bit UART with 115200 baud, <br>
                    1 stop bits and N parity";
            MESSAGES 
            {
            }
         }
      }
      SIMULATION 
      {
         DISPLAY 
         {
            SIGNAL a
            {
               name = "  Bus Interface";
               format = "Divider";
            }
            SIGNAL b
            {
               name = "chipselect";
            }
            SIGNAL c
            {
               name = "address";
               radix = "hexadecimal";
            }
            SIGNAL d
            {
               name = "writedata";
               radix = "hexadecimal";
            }
            SIGNAL e
            {
               name = "readdata";
               radix = "hexadecimal";
            }
            SIGNAL f
            {
               name = "  Internals";
               format = "Divider";
            }
            SIGNAL g
            {
               name = "tx_ready";
            }
            SIGNAL h
            {
               name = "tx_data";
               radix = "ascii";
            }
            SIGNAL i
            {
               name = "rx_char_ready";
            }
            SIGNAL j
            {
               name = "rx_data";
               radix = "ascii";
            }
         }
      }
      WIZARD_SCRIPT_ARGUMENTS 
      {
         baud = "115200";
         data_bits = "8";
         fixed_baud = "1";
         parity = "N";
         stop_bits = "1";
         use_cts_rts = "0";
         use_eop_register = "0";
         sim_true_baud = "0";
         sim_char_stream = "";
      }
      HDL_INFO 
      {
         Simulation_HDL_Files = "__PROJECT_DIRECTORY__/sopc_sim/uart_OSView_rx_stimulus_source_character_source_rom_module.vhd";
         Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/uart_OSView.vhd";
      }
      PORT_WIRING 
      {
         PORT rxd
         {
            direction = "input";
            width = "1";
         }
         PORT txd
         {
            direction = "output";
            width = "1";
         }
      }
   }
}