freedes.vhd.txt

DES 加密算法的VHDL和VERILOG 源程序及其TESTBENCH。

          dout		:out std_logic_vector (63 downto 0);
          dout_valid	:out std_logic
         );
end des_round;


architecture arch_des_round of des_round is
begin

  process (clk, reset, stall, key_in, din, din_valid, encrypt_IN, encrypt_shift, decrypt_shift)
    variable key        :std_logic_vector (47 downto 0);
    variable data_ep    :std_logic_vector (47 downto 0);
    variable data_sbox  :std_logic_vector (31 downto 0);
    variable data_pbox  :std_logic_vector (31 downto 0);
  begin
    if reset='1' then
      key_out <= "00000000000000000000000000000000000000000000000000000000";
      dout  <= "0000000000000000000000000000000000000000000000000000000000000000";
      dout_valid <= '0';
	  encrypt_out <= '0';
    elsif clk'event and clk='1' then
      if stall='0' then
        -- Handle the key
        encrypt_out <= encrypt_in;
        key_out   <= key_in;
        if encrypt_in='1' then
          key       := des_cp(des_keyshift(key_in,encrypt_shift));
        else
          key       := des_cp(des_keyshift(key_in,decrypt_shift));
        end if;        

        -- Handle the data
        data_ep   := des_ep(din(31 downto 0)) xor key;
        data_sbox := des_sbox(data_ep);
        data_pbox := des_pbox(data_sbox) xor din(63 downto 32);
        dout      <= din(31 downto 0) & data_pbox;

        dout_valid <= din_valid;
      end if;
    end if;
  end process;

end arch_des_round;


----------------------------------------------------------------------------
----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library work;
use work.des_lib.all;

entity des_fast is
    port (clk		:in std_logic;
          reset		:in std_logic;
          stall		:in std_logic;

	  encrypt	:in std_logic;
          key_in	:in std_logic_vector (55 downto 0);
          din		:in std_logic_vector (63 downto 0);
          din_valid     :in std_logic;

          dout		:out std_logic_vector (63 downto 0);
          dout_valid	:out std_logic;
          key_out	:out std_logic_vector (55 downto 0)
         );
end des_fast;

architecture arch_des_fast of des_fast is
  signal r01_key_out	:std_logic_vector (55 downto 0) := "00000000000000000000000000000000000000000000000000000000";
  signal r02_key_out	:std_logic_vector (55 downto 0) := "00000000000000000000000000000000000000000000000000000000";
  signal r03_key_out	:std_logic_vector (55 downto 0) := "00000000000000000000000000000000000000000000000000000000";
  signal r04_key_out	:std_logic_vector (55 downto 0) := "00000000000000000000000000000000000000000000000000000000";
  signal r05_key_out	:std_logic_vector (55 downto 0) := "00000000000000000000000000000000000000000000000000000000";
  signal r06_key_out	:std_logic_vector (55 downto 0) := "00000000000000000000000000000000000000000000000000000000";
  signal r07_key_out	:std_logic_vector (55 downto 0) := "00000000000000000000000000000000000000000000000000000000";
  signal r08_key_out	:std_logic_vector (55 downto 0) := "00000000000000000000000000000000000000000000000000000000";
  signal r09_key_out	:std_logic_vector (55 downto 0) := "00000000000000000000000000000000000000000000000000000000";
  signal r10_key_out	:std_logic_vector (55 downto 0) := "00000000000000000000000000000000000000000000000000000000";
  signal r11_key_out	:std_logic_vector (55 downto 0) := "00000000000000000000000000000000000000000000000000000000";
  signal r12_key_out	:std_logic_vector (55 downto 0) := "00000000000000000000000000000000000000000000000000000000";
  signal r13_key_out	:std_logic_vector (55 downto 0) := "00000000000000000000000000000000000000000000000000000000";
  signal r14_key_out	:std_logic_vector (55 downto 0) := "00000000000000000000000000000000000000000000000000000000";
  signal r15_key_out	:std_logic_vector (55 downto 0) := "00000000000000000000000000000000000000000000000000000000";
  signal r16_key_out	:std_logic_vector (55 downto 0) := "00000000000000000000000000000000000000000000000000000000";

  signal r01_dout	:std_logic_vector (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000";
  signal r02_dout	:std_logic_vector (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000";
  signal r03_dout	:std_logic_vector (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000";
  signal r04_dout	:std_logic_vector (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000";
  signal r05_dout	:std_logic_vector (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000";
  signal r06_dout	:std_logic_vector (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000";
  signal r07_dout	:std_logic_vector (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000";
  signal r08_dout	:std_logic_vector (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000";
  signal r09_dout	:std_logic_vector (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000";
  signal r10_dout	:std_logic_vector (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000";
  signal r11_dout	:std_logic_vector (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000";
  signal r12_dout	:std_logic_vector (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000";
  signal r13_dout	:std_logic_vector (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000";
  signal r14_dout	:std_logic_vector (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000";
  signal r15_dout	:std_logic_vector (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000";
  signal r16_dout	:std_logic_vector (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000";

  signal r01_dout_valid :std_logic := '0';
  signal r02_dout_valid :std_logic := '0';
  signal r03_dout_valid :std_logic := '0';
  signal r04_dout_valid :std_logic := '0';
  signal r05_dout_valid :std_logic := '0';
  signal r06_dout_valid :std_logic := '0';
  signal r07_dout_valid :std_logic := '0';
  signal r08_dout_valid :std_logic := '0';
  signal r09_dout_valid :std_logic := '0';
  signal r10_dout_valid :std_logic := '0';
  signal r11_dout_valid :std_logic := '0';
  signal r12_dout_valid :std_logic := '0';
  signal r13_dout_valid :std_logic := '0';
  signal r14_dout_valid :std_logic := '0';
  signal r15_dout_valid :std_logic := '0';

  signal r01_encrypt_out:std_logic := '0';
  signal r02_encrypt_out:std_logic := '0';
  signal r03_encrypt_out:std_logic := '0';
  signal r04_encrypt_out:std_logic := '0';
  signal r05_encrypt_out:std_logic := '0';
  signal r06_encrypt_out:std_logic := '0';
  signal r07_encrypt_out:std_logic := '0';
  signal r08_encrypt_out:std_logic := '0';
  signal r09_encrypt_out:std_logic := '0';
  signal r10_encrypt_out:std_logic := '0';
  signal r11_encrypt_out:std_logic := '0';
  signal r12_encrypt_out:std_logic := '0';
  signal r13_encrypt_out:std_logic := '0';
  signal r14_encrypt_out:std_logic := '0';
  signal r15_encrypt_out:std_logic := '0';
  signal r16_encrypt_out:std_logic := '0';

  signal encrypt_shift1 :std_logic_vector (4 downto 0) := "00000";
  signal encrypt_shift2 :std_logic_vector (4 downto 0) := "00000";
  signal encrypt_shift3 :std_logic_vector (4 downto 0) := "00000";
  signal encrypt_shift4 :std_logic_vector (4 downto 0) := "00000";
  signal encrypt_shift5 :std_logic_vector (4 downto 0) := "00000";
  signal encrypt_shift6 :std_logic_vector (4 downto 0) := "00000";
  signal encrypt_shift7 :std_logic_vector (4 downto 0) := "00000";
  signal encrypt_shift8 :std_logic_vector (4 downto 0) := "00000";
  signal encrypt_shift9 :std_logic_vector (4 downto 0) := "00000";
  signal encrypt_shift10 :std_logic_vector (4 downto 0) := "00000";
  signal encrypt_shift11 :std_logic_vector (4 downto 0) := "00000";
  signal encrypt_shift12 :std_logic_vector (4 downto 0) := "00000";
  signal encrypt_shift13 :std_logic_vector (4 downto 0) := "00000";
  signal encrypt_shift14 :std_logic_vector (4 downto 0) := "00000";
  signal encrypt_shift15 :std_logic_vector (4 downto 0) := "00000";
  signal encrypt_shift16 :std_logic_vector (4 downto 0) := "00000";
  
  signal decrypt_shift1 :std_logic_vector (4 downto 0) := "00000";
  signal decrypt_shift2 :std_logic_vector (4 downto 0) := "00000";
  signal decrypt_shift3 :std_logic_vector (4 downto 0) := "00000";
  signal decrypt_shift4 :std_logic_vector (4 downto 0) := "00000";
  signal decrypt_shift5 :std_logic_vector (4 downto 0) := "00000";
  signal decrypt_shift6 :std_logic_vector (4 downto 0) := "00000";
  signal decrypt_shift7 :std_logic_vector (4 downto 0) := "00000";
  signal decrypt_shift8 :std_logic_vector (4 downto 0) := "00000";
  signal decrypt_shift9 :std_logic_vector (4 downto 0) := "00000";
  signal decrypt_shift10 :std_logic_vector (4 downto 0) := "00000";
  signal decrypt_shift11 :std_logic_vector (4 downto 0) := "00000";
  signal decrypt_shift12 :std_logic_vector (4 downto 0) := "00000";
  signal decrypt_shift13 :std_logic_vector (4 downto 0) := "00000";
  signal decrypt_shift14 :std_logic_vector (4 downto 0) := "00000";
  signal decrypt_shift15 :std_logic_vector (4 downto 0) := "00000";
  signal decrypt_shift16 :std_logic_vector (4 downto 0) := "00000";
  
  signal key_in_r	:std_logic_vector (55 downto 0) := "00000000000000000000000000000000000000000000000000000000";
  signal din_r		:std_logic_vector (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000";
  signal din_valid_r   	:std_logic := '0';

begin
  -- Register the inputs
  process (reset, clk, key_in, din, din_valid)
  begin
    if reset='1' then
      key_in_r <= "00000000000000000000000000000000000000000000000000000000";
      din_r    <= "0000000000000000000000000000000000000000000000000000000000000000";
      din_valid_r <= '0';
    elsif clk'event and clk='1' then
      key_in_r <= key_in;
      din_r    <= des_ip(din);
      din_valid_r <= din_valid;
    end if;
  end process;

  encrypt_shift1  <= "00001"; decrypt_shift1  <= "00000";
  encrypt_shift2  <= "00010"; decrypt_shift2  <= "11011";
  encrypt_shift3  <= "00100"; decrypt_shift3  <= "11001";
  encrypt_shift4  <= "00110"; decrypt_shift4  <= "10111";
  encrypt_shift5  <= "01000"; decrypt_shift5  <= "10101";
  encrypt_shift6  <= "01010"; decrypt_shift6  <= "10011";
  encrypt_shift7  <= "01100"; decrypt_shift7  <= "10001";
  encrypt_shift8  <= "01110"; decrypt_shift8  <= "01111";
  encrypt_shift9  <= "01111"; decrypt_shift9  <= "01110";
  encrypt_shift10 <= "10001"; decrypt_shift10 <= "01100";
  encrypt_shift11 <= "10011"; decrypt_shift11 <= "01010";
  encrypt_shift12 <= "10101"; decrypt_shift12 <= "01000";
  encrypt_shift13 <= "10111"; decrypt_shift13 <= "00110";
  encrypt_shift14 <= "11001"; decrypt_shift14 <= "00100";
  encrypt_shift15 <= "11011"; decrypt_shift15 <= "00010";
  encrypt_shift16 <= "00000"; decrypt_shift16 <= "00001";