📄 freedes.vhd.txt
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----------------------------------------------------------------------------
----------------------------------------------------------------------------
-- The Free IP Project
-- VHDL DES Core
-- (c) 1999, The Free IP Project and David Kessner
--
--
-- Warning: This software probably falls under the jurisdiction of some
-- cryptography import/export laws. Don't import/export this
-- file (or products that use this file) unless you've worked
-- out all the legal issues. Don't say we didn't warn you!
--
--
-- FREE IP GENERAL PUBLIC LICENSE
-- TERMS AND CONDITIONS FOR USE, COPYING, DISTRIBUTION, AND MODIFICATION
--
-- 1. You may copy and distribute verbatim copies of this core, as long
-- as this file, and the other associated files, remain intact and
-- unmodified. Modifications are outlined below. Also, see the
-- import/export warning above for further restrictions on
-- distribution.
-- 2. You may use this core in any way, be it academic, commercial, or
-- military. Modified or not. See, again, the import/export warning
-- above.
-- 3. Distribution of this core must be free of charge. Charging is
-- allowed only for value added services. Value added services
-- would include copying fees, modifications, customizations, and
-- inclusion in other products.
-- 4. If a modified source code is distributed, the original unmodified
-- source code must also be included (or a link to the Free IP web
-- site). In the modified source code there must be clear
-- identification of the modified version.
-- 5. Visit the Free IP web site for additional information.
--
----------------------------------------------------------------------------
----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
package des_lib is
component des_fast
port (clk :in std_logic;
reset :in std_logic;
stall :in std_logic;
encrypt :in std_logic; -- 1=encrypt, 0=decrypt
key_in :in std_logic_vector (55 downto 0);
din :in std_logic_vector (63 downto 0);
din_valid :in std_logic;
dout :out std_logic_vector (63 downto 0);
dout_valid :out std_logic;
key_out :out std_logic_vector (55 downto 0)
);
end component;
component des_small
port (clk :in std_logic;
reset :in std_logic;
encrypt :in std_logic;
key_in :in std_logic_vector (55 downto 0);
din :in std_logic_vector (63 downto 0);
din_valid :in std_logic;
busy :buffer std_logic;
dout :out std_logic_vector (63 downto 0);
dout_valid :out std_logic
);
end component;
component des_round
port (clk :in std_logic;
reset :in std_logic;
stall :in std_logic;
encrypt_in :in std_logic;
encrypt_shift :in std_logic_vector (4 downto 0);
decrypt_shift :in std_logic_vector (4 downto 0);
key_in :in std_logic_vector (55 downto 0);
din :in std_logic_vector (63 downto 0);
din_valid :in std_logic;
encrypt_out :out std_logic;
key_out :out std_logic_vector (55 downto 0);
dout :out std_logic_vector (63 downto 0);
dout_valid :out std_logic
);
end component;
-- Inital permutation
function des_ip(din :std_logic_vector(63 downto 0))
return std_logic_vector;
-- Final permutation
function des_fp(din :std_logic_vector(63 downto 0))
return std_logic_vector;
-- Key permutation, converts a 64 bit key into a 56 bit key, ignoring parity
function des_kp(din :std_logic_vector (63 downto 0))
return std_logic_vector;
-- Compression Permutation, converts a 56 bit key into a 48 bits.
function des_cp(din :std_logic_vector (55 downto 0))
return std_logic_vector;
-- Expansion permutation
function des_ep(din :std_logic_vector (31 downto 0))
return std_logic_vector;
-- S-Box Substitution, 48 bits in, 32 bits out.
function des_sbox(din :std_logic_vector (47 downto 0))
return std_logic_vector;
-- P-Box Permutation
function des_pbox(din :std_logic_vector (31 downto 0))
return std_logic_vector;
-- Key Shift
function des_keyshift (din :std_logic_vector (55 downto 0);
n :std_logic_vector (4 downto 0))
return std_logic_vector;
end des_lib;
----------------------------------------------------------------------------
----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library work;
use work.des_lib.all;
package body des_lib is
--------------------------------------------------------
-- Inital permutation
function des_ip(din :std_logic_vector(63 downto 0))
return std_logic_vector is
variable val :std_logic_vector (63 downto 0);
begin
val := din(64-58) & din(64-50) & din(64-42) & din(64-34) & din(64-26) & din(64-18) & din(64-10) & din(64- 2) &
din(64-60) & din(64-52) & din(64-44) & din(64-36) & din(64-28) & din(64-20) & din(64-12) & din(64- 4) &
din(64-62) & din(64-54) & din(64-46) & din(64-38) & din(64-30) & din(64-22) & din(64-14) & din(64- 6) &
din(64-64) & din(64-56) & din(64-48) & din(64-40) & din(64-32) & din(64-24) & din(64-16) & din(64- 8) &
din(64-57) & din(64-49) & din(64-41) & din(64-33) & din(64-25) & din(64-17) & din(64- 9) & din(64- 1) &
din(64-59) & din(64-51) & din(64-43) & din(64-35) & din(64-27) & din(64-19) & din(64-11) & din(64- 3) &
din(64-61) & din(64-53) & din(64-45) & din(64-37) & din(64-29) & din(64-21) & din(64-13) & din(64- 5) &
din(64-63) & din(64-55) & din(64-47) & din(64-39) & din(64-31) & din(64-23) & din(64-15) & din(64- 7);
return val;
end des_ip;
--------------------------------------------------------
-- Final permutation
function des_fp(din :std_logic_vector(63 downto 0))
return std_logic_vector is
variable val :std_logic_vector (63 downto 0);
begin
val := din(64-40) & din(64- 8) & din(64-48) & din(64-16) & din(64-56) & din(64-24) & din(64-64) & din(64-32) &
din(64-39) & din(64- 7) & din(64-47) & din(64-15) & din(64-55) & din(64-23) & din(64-63) & din(64-31) &
din(64-38) & din(64- 6) & din(64-46) & din(64-14) & din(64-54) & din(64-22) & din(64-62) & din(64-30) &
din(64-37) & din(64- 5) & din(64-45) & din(64-13) & din(64-53) & din(64-21) & din(64-61) & din(64-29) &
din(64-36) & din(64- 4) & din(64-44) & din(64-12) & din(64-52) & din(64-20) & din(64-60) & din(64-28) &
din(64-35) & din(64- 3) & din(64-43) & din(64-11) & din(64-51) & din(64-19) & din(64-59) & din(64-27) &
din(64-34) & din(64- 2) & din(64-42) & din(64-10) & din(64-50) & din(64-18) & din(64-58) & din(64-26) &
din(64-33) & din(64- 1) & din(64-41) & din(64- 9) & din(64-49) & din(64-17) & din(64-57) & din(64-25);
return val;
end des_fp;
--------------------------------------------------------
-- Key permutation, converts a 64 bit key into a 56 bit key, ignoring parity
function des_kp(din :std_logic_vector (63 downto 0))
return std_logic_vector is
variable val :std_logic_vector (55 downto 0);
begin
val := din(64-57) & din(64-49) & din(64-41) & din(64-33) & din(64-25) & din(64-17) & din(64- 9) & din(64- 1) &
din(64-58) & din(64-50) & din(64-42) & din(64-34) & din(64-26) & din(64-18) & din(64-10) & din(64- 2) &
din(64-59) & din(64-51) & din(64-43) & din(64-35) & din(64-27) & din(64-19) & din(64-11) & din(64- 3) &
din(64-60) & din(64-52) & din(64-44) & din(64-36) &
din(64-63) & din(64-55) & din(64-47) & din(64-39) & din(64-31) & din(64-23) & din(64-15) & din(64- 7) &
din(64-62) & din(64-54) & din(64-46) & din(64-38) & din(64-30) & din(64-22) & din(64-14) & din(64- 6) &
din(64-61) & din(64-53) & din(64-45) & din(64-37) & din(64-29) & din(64-21) & din(64-13) & din(64- 5) &
din(64-28) & din(64-20) & din(64-12) & din(64- 4);
return val;
end des_kp;
--------------------------------------------------------
-- Compression Permutation, converts a 56 bit key into a 48 bits.
function des_cp(din :std_logic_vector (55 downto 0))
return std_logic_vector is
variable val :std_logic_vector (47 downto 0);
begin
val := din(56-14) & din(56-17) & din(56-11) & din(56-24) & din(56- 1) & din(56- 5) &
din(56- 3) & din(56-28) & din(56-15) & din(56- 6) & din(56-21) & din(56-10) &
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