This thesis is devoted to several efficient VLSI architecture design issues in errorcorrecting
codi - 资源详细说明
This thesis is devoted to several efficient VLSI architecture design issues in errorcorrecting
coding, including finite field arithmetic, (Generalized) Low-Density Parity-
Check (LDPC) codes, and Reed-Solomon codes.
This thesis is devoted to several efficient VLSI architecture design issues in errorcorrecting
codi - 源码文件列表