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Transition-Time

  • Transition-Time Optimization for Switched-Mode Dynamical Systems

    Transition-Time Optimization for Switched-Mode Dynamical Systems

    标签: Transition-Time Switched-Mode Optimization Dynamical

    上传时间: 2017-09-28

    上传用户:xinyuzhiqiwuwu

  • 二极管导通开关稳压器引发的故障时间

      Most circuit designers are familiar with diode dynamiccharacteristics such as charge storage, voltage dependentcapacitance and reverse recovery time. Less commonlyacknowledged and manufacturer specifi ed is diode forwardturn-on time. This parameter describes the timerequired for a diode to turn on and clamp at its forwardvoltage drop. Historically, this extremely short time, unitsof nanoseconds, has been so small that user and vendoralike have essentially ignored it. It is rarely discussed andalmost never specifi ed. Recently, switching regulator clockrate and transition time have become faster, making diodeturn-on time a critical issue. Increased clock rates aremandated to achieve smaller magnetics size; decreasedtransition times somewhat aid overall effi ciency but areprincipally needed to minimize IC heat rise. At clock speedsbeyond about 1MHz, transition time losses are the primarysource of die heating.

    标签: 二极管 导通 开关稳压器

    上传时间: 2013-10-10

    上传用户:谁偷了我的麦兜

  • Input Signal Rise and Fall Tim

    All inputs of the C16x family have Schmitt-Trigger input characteristics. These Schmitt-Triggers are intended to always provide proper internal low and high levels, even if anundefined voltage level (between TTL-VIL and TTL-VIH) is externally applied to the pin.The hysteresis of these inputs, however, is very small, and can not be properly used in anapplication to suppress signal noise, and to shape slow rising/falling input transitions.Thus, it must be taken care that rising/falling input signals pass the undefined area of theTTL-specification between VIL and VIH with a sufficient rise/fall time, as generally usualand specified for TTL components (e.g. 74LS series: gates 1V/us, clock inputs 20V/us).The effect of the implemented Schmitt-Trigger is that even if the input signal remains inthe undefined area, well defined low/high levels are generated internally. Note that allinput signals are evaluated at specific sample points (depending on the input and theperipheral function connected to it), at that signal transitions are detected if twoconsecutive samples show different levels. Thus, only the current level of an input signalat these sample points is relevant, that means, the necessary rise/fall times of the inputsignal is only dependant on the sample rate, that is the distance in time between twoconsecutive evaluation time points. If an input signal, for instance, is sampled throughsoftware every 10us, it is irrelevant, which input level would be seen between thesamples. Thus, it would be allowable for the signal to take 10us to pass through theundefined area. Due to the sample rate of 10us, it is assured that only one sample canoccur while the signal is within the undefined area, and no incorrect transition will bedetected. For inputs which are connected to a peripheral function, e.g. capture inputs, thesample rate is determined by the clock cycle of the peripheral unit. In the case of theCAPCOM unit this means a sample rate of 400ns @ 20MHz CPU clock. This requiresinput signals to pass through the undefined area within these 400ns in order to avoidmultiple capture events.For input signals, which do not provide the required rise/fall times, external circuitry mustbe used to shape the signal transitions.In the attached diagram, the effect of the sample rate is shown. The numbers 1 to 5 in thediagram represent possible sample points. Waveform a) shows the result if the inputsignal transition time through the undefined TTL-level area is less than the time distancebetween the sample points (sampling at 1, 2, 3, and 4). Waveform b) can be the result ifthe sampling is performed more than once within the undefined area (sampling at 1, 2, 5,3, and 4).Sample points:1. Evaluation of the signal clearly results in a low level2. Either a low or a high level can be sampled here. If low is sampled, no transition willbe detected. If the sample results in a high level, a transition is detected, and anappropriate action (e.g. capture) might take place.3. Evaluation here clearly results in a high level. If the previous sample 2) had alreadydetected a high, there is no change. If the previous sample 2) showed a low, atransition from low to high is detected now.

    标签: Signal Input Fall Rise

    上传时间: 2013-10-23

    上传用户:copu

  • We present a particle filter construction for a system that exhibits time-scale separation. The sep

    We present a particle filter construction for a system that exhibits time-scale separation. The separation of time-scales allows two simplifications that we exploit: i) The use of the averaging principle for the dimensional reduction of the system needed to solve for each particle and ii) the factorization of the transition probability which allows the Rao-Blackwellization of the filtering step. Both simplifications can be implemented using the coarse projective integration framework. The resulting particle filter is faster and has smaller variance than the particle filter based on the original system. The convergence of the new particle filter to the analytical filter for the original system is proved and some numerical results are provided.

    标签: construction separation time-scale particle

    上传时间: 2016-01-02

    上传用户:fhzm5658

  • Space-Time+Processing

    Driven by the desire to boost the quality of service of wireless systems closer to that afforded by wireline systems, space-time processing for multiple-input multiple-output (MIMO) wireless communications research has drawn remarkable interest in recent years. Excit- ing theoretical advances, complemented by rapid transition of research results to industry products and services, have created a vibrant and growing area that is already established by all counts. This offers a good opportunity to reflect on key developments in the area during the past decade and also outline emerging trends.

    标签: Space-Time Processing

    上传时间: 2020-05-31

    上传用户:shancjb

  • stbc_ofdm(time)

    从时域分析比较了ofdm和stbc与ofdm结合的性能差别-from time-domain analysis and comparison of OFDM stbc OFDM combined wi

    标签: stbc_ofdm time

    上传时间: 2013-06-05

    上传用户:caozhizhi

  • ADC转换器技术用语 (A/D Converter Defi

    ANALOG INPUT BANDWIDTH is a measure of the frequencyat which the reconstructed output fundamental drops3 dB below its low frequency value for a full scale input. Thetest is performed with fIN equal to 100 kHz plus integer multiplesof fCLK. The input frequency at which the output is −3dB relative to the low frequency input signal is the full powerbandwidth.APERTURE JITTER is the variation in aperture delay fromsample to sample. Aperture jitter shows up as input noise.APERTURE DELAY See Sampling Delay.BOTTOM OFFSET is the difference between the input voltagethat just causes the output code to transition to the firstcode and the negative reference voltage. Bottom Offset isdefined as EOB = VZT–VRB, where VZT is the first code transitioninput voltage and VRB is the lower reference voltage.Note that this is different from the normal Zero Scale Error.CONVERSION LATENCY See PIPELINE DELAY.CONVERSION TIME is the time required for a completemeasurement by an analog-to-digital converter. Since theConversion Time does not include acquisition time, multiplexerset up time, or other elements of a complete conversioncycle, the conversion time may be less than theThroughput Time.DC COMMON-MODE ERROR is a specification which appliesto ADCs with differential inputs. It is the change in theoutput code that occurs when the analog voltages on the twoinputs are changed by an equal amount. It is usually expressed in LSBs.

    标签: Converter Defi ADC 转换器

    上传时间: 2013-11-11

    上传用户:pans0ul

  • HT47R20A-1时基(Time Base)使用介绍

    HT47R20A-1时基(Time Base)使用介绍 HT47 系列单片机的时基可提供一个周期性超时时间周期以产生规则性的内部中断。时基的时钟来源可由掩膜选择设定为WDT 时钟、RTC 时钟或指令时钟(系统时钟/4);其超时时间范围可由掩膜选择设定为“时钟来源”/212~“时钟来源”/215。如果时基发生超时现象,则其对应的中断请求标志(TBF)会被置位,如果中断允许,则产生一个中断服务到08H 的地址。

    标签: Base Time HT 47

    上传时间: 2013-11-15

    上传用户:13925096126

  • 介绍C16x系列微控制器的输入信号升降时序图及特性

    All inputs of the C16x family have Schmitt-Trigger input characteristics. These Schmitt-Triggers are intended to always provide proper internal low and high levels, even if anundefined voltage level (between TTL-VIL and TTL-VIH) is externally applied to the pin.The hysteresis of these inputs, however, is very small, and can not be properly used in anapplication to suppress signal noise, and to shape slow rising/falling input transitions.Thus, it must be taken care that rising/falling input signals pass the undefined area of theTTL-specification between VIL and VIH with a sufficient rise/fall time, as generally usualand specified for TTL components (e.g. 74LS series: gates 1V/us, clock inputs 20V/us).The effect of the implemented Schmitt-Trigger is that even if the input signal remains inthe undefined area, well defined low/high levels are generated internally. Note that allinput signals are evaluated at specific sample points (depending on the input and theperipheral function connected to it), at that signal transitions are detected if twoconsecutive samples show different levels. Thus, only the current level of an input signalat these sample points is relevant, that means, the necessary rise/fall times of the inputsignal is only dependant on the sample rate, that is the distance in time between twoconsecutive evaluation time points. If an input signal, for instance, is sampled throughsoftware every 10us, it is irrelevant, which input level would be seen between thesamples. Thus, it would be allowable for the signal to take 10us to pass through theundefined area. Due to the sample rate of 10us, it is assured that only one sample canoccur while the signal is within the undefined area, and no incorrect transition will bedetected. For inputs which are connected to a peripheral function, e.g. capture inputs, thesample rate is determined by the clock cycle of the peripheral unit. In the case of theCAPCOM unit this means a sample rate of 400ns @ 20MHz CPU clock. This requiresinput signals to pass through the undefined area within these 400ns in order to avoidmultiple capture events.

    标签: C16x 微控制器 输入信号 时序图

    上传时间: 2014-04-02

    上传用户:han_zh

  • PICMG_COM_0_R2_0COMe规范--原文资料

    A Computer-On-Module, or COM, is a Module with all components necessary for a bootable host computer, packaged as a super component. A COM requires a Carrier Board to bring out I/O and to power up. COMs are used to build single board computer solutions and offer OEMs fast time-to-market with reduced development cost. Like integrated circuits, they provide OEMs with significant freedom in meeting form-fit-function requirements. For all these reasons the COM methodology has gained much popularity with OEMs in the embedded industry. COM Express® is an open industry standard for Computer-On-Modules. It is designed to be future proof and to provide a smooth transition path from legacy parallel interfaces to LVDS (Low Voltage Differential Signaling) interfaces. These include the PCI bus and parallel ATA on the one hand and PCI Express and Serial ATA on the other hand.

    标签: PICMG_COM COMe

    上传时间: 2013-11-04

    上传用户:Wwill