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Easily

  • MAXQUSBJTAGOW评估板软件

    MAXQUSBJTAGOW评估板软件:关键特性 Easily Load and Debug Code Interface Provides In-Application Debugging Features Step-by-Step Execution Tracing Breakpointing by Code Address, Data Memory Address, or Register Access Data Memory View and Edit Supports Logic Levels from 1.1V to 3.6V Supports JTAG and 1-Wire Protocols Each Adapter Has Its Own Unique Serial ID, Allowing Multiple Adapters to be Connected Without COM Port Conflicts Has In-Field Upgradable Capability if Firmware Needs to be Upgraded Enclosure Protects from Shorts and ESD

    标签: MAXQUSBJTAGOW 评估板 软件

    上传时间: 2013-10-23

    上传用户:teddysha

  • MAXQUSBJTAGOW评估板软件

    MAXQUSBJTAGOW评估板软件:关键特性 Easily Load and Debug Code Interface Provides In-Application Debugging Features Step-by-Step Execution Tracing Breakpointing by Code Address, Data Memory Address, or Register Access Data Memory View and Edit Supports Logic Levels from 1.1V to 3.6V Supports JTAG and 1-Wire Protocols Each Adapter Has Its Own Unique Serial ID, Allowing Multiple Adapters to be Connected Without COM Port Conflicts Has In-Field Upgradable Capability if Firmware Needs to be Upgraded Enclosure Protects from Shorts and ESD

    标签: MAXQUSBJTAGOW 评估板 软件

    上传时间: 2013-11-23

    上传用户:truth12

  • XAPP380 -利用CoolRunner-II CPLD创建交叉点开关

      This application note provides a functional description of VHDL source code for a N x N DigitalCrosspoint Switch. The code is designed with eight inputs and eight outputs in order to targetthe 128-macrocell CoolRunner™-II CPLD device but can be Easily expanded to target higherdensity devices. To obtain the VHDL source code described in this document, go to sectionVHDL Code, page 5 for instructions.

    标签: CoolRunner-II XAPP CPLD 380

    上传时间: 2013-10-26

    上传用户:kiklkook

  • PLD对FPGA数据加密

    SRAM-based FPGAs are non-volatile devices. Upon powerup, They are required to be programmed from an external source. This procedure allows anyone to Easily monitor the bit-stream, and clone the device. The problem then becomes how can you effectively protect your intellectual property from others in an architecture where the part is externally programmed?

    标签: FPGA PLD 数据加密

    上传时间: 2013-10-19

    上传用户:磊子226

  • 基于Verilog HDL设计的多功能数字钟

    本文利用Verilog HDL 语言自顶向下的设计方法设计多功能数字钟,突出了其作为硬件描述语言的良好的可读性、可移植性和易理解等优点,并通过Altera QuartusⅡ 4.1 和ModelSim SE 6.0 完成综合、仿真。此程序通过下载到FPGA 芯片后,可应用于实际的数字钟显示中。 关键词:Verilog HDL;硬件描述语言;FPGA Abstract: In this paper, the process of designing multifunctional digital clock by the Verilog HDL top-down design method is presented, which has shown the readability, portability and Easily understanding of Verilog HDL as a hard description language. Circuit synthesis and simulation are performed by Altera QuartusⅡ 4.1 and ModelSim SE 6.0. The program can be used in the truly digital clock display by downloading to the FPGA chip. Keywords: Verilog HDL;hardware description language;FPGA

    标签: Verilog HDL 多功能 数字

    上传时间: 2013-11-09

    上传用户:hz07104032

  • UART 4 UART参考设计,Xilinx提供VHDL代码

    UART 4 UART参考设计,Xilinx提供VHDL代码 uart_vhdl This zip file contains the following folders:  \vhdl_source  -- Source VHDL files:      uart.vhd  - top level file      txmit.vhd - transmit portion of uart      rcvr.vhd -  - receive portion of uart \vhdl_testfixture  -- VHDL Testbench files. This files only include the testbench behavior, they         do not instantiate the DUT. This can Easily be done in a top-level VHDL          file or a schematic. This folder contains the following files:      txmit_tb.vhd  -- Test bench for txmit.vhd.      rcvr_tf.vhd  -- Test bench for rcvr.vhd.

    标签: UART Xilinx VHDL 参考设计

    上传时间: 2013-11-01

    上传用户:18862121743

  • 手机文件浏览器 Here are the sources to SMan v1.2c 1.2 is a major jump from v1.1. You will see this from the

    手机文件浏览器 Here are the sources to SMan v1.2c 1.2 is a major jump from v1.1. You will see this from the way the code has been restructured into multiple files. It also supports flip closed. However, to my chagrin, I made the mistake of assuming there will only be one flip closed view. :( That s changed in v1.3 :) 1.3 supports multiple flip closed views that can be Easily added into SMan.

    标签: from 1.2 the sources

    上传时间: 2015-03-30

    上传用户:彭玖华

  • LIBSVM is an integrated software for support vector classification. LIBSVM provides a simple interfa

    LIBSVM is an integrated software for support vector classification. LIBSVM provides a simple interface where users can Easily link it with their own programs.

    标签: LIBSVM classification integrated software

    上传时间: 2015-04-04

    上传用户:alan-ee

  • 项目描述: Trickster Streaming Server is a pure Perl MP3 streaming server with a simple Web interface t

    项目描述: Trickster Streaming Server is a pure Perl MP3 streaming server with a simple Web interface that allows you to manipulate and browse the queue. The queue management API is done in a fairly simple UNIX manner, and can be Easily extended. Trickster Streaming Server是一个具有简单 Web接口的纯 Perl MP3流服务器,它让你操作并浏览队列。这个队列管理 API 用一种相当简单的UNIX方式来做,并能被容易的扩展。

    标签: Trickster Streaming interface streaming

    上传时间: 2013-12-13

    上传用户:lz4v4

  • 自制51编程器 I have build my own programmer. This device can program the AT89C51 and works with it. So i

    自制51编程器 I have build my own programmer. This device can program the AT89C51 and works with it. So it can Easily be adapted to programming other devices by itself. The Atmel Flash devices are ideal for developing, since they can be reprogrammed easy, often and fast. You need only 1 or 2 devices in low cost plastic case for developing. In contrast you need 10 or more high cost windowed devices if you must develop with EPROM devices (e.g. Phillips 87C751).

    标签: programmer program device build

    上传时间: 2015-05-11

    上传用户:sdq_123