PCI（Peripheral Component Interconnect）局部总线是微型计算机中处理器、存储器与外围控制部件、扩展卡之间的互连接口，由于其速度快、可靠性高、成本低、兼容性好等特点，在各种计算机总线标准占有重要地位，基于PCI标准的接口设计已经成为相关项目开发中的一个重要的选择。 目前，现场可编程门阵列FPGA（Field Programmable Gates）得到了广泛应用。由于其具有规模大，开发过程投资小，可反复编程，且支持软硬件协同设计等特点，因此已逐步成为复杂数字硬件电路设计的首选。 PCI接口的开发有多种方法，主要有两种：一是使用专用接口芯片，二是使用可编程逻辑器件，如FPGA。本论文基于成本和实际需要的考虑，采用第二种方法进行设计。 本论文采用自上而下（Top-To-DOWN）和模块化的设计方法，使用FPGA和硬件描述语言（VHDL和Verilog HDL）设计了一个PCI接口核，并通过自行设计的试验板对其进行验证。为使设计准确可靠，在具体模块的设计中广泛采用流水线技术和状态机的方法。 论文最终设计完成了一个33M32位的PCI主从接口，并把它作为以NIOSⅡ为核心的SOPC片内外设，与通用计算机成功进行了通讯。 论文对PCI接口进行了功能仿真，仿真结果和PCI协议的要求一致，表明本论文设计正确。把设计下载进FPGA芯片EP2C8Q208C7之后，论文给出了使用SIGNALTAPⅡ观察到的信号实际波形，波形显示PCI接口能够满足本设计中系统的需要。本文最后还给出试验板的具体设计步骤及驱动程序的安装。
上传时间： 2013-07-28
上传用户：372825274
英文描述： Synchronous Up/DOWN Decade Counters(single clock line) 中文描述： 同步向上/向下十年计数器（单时钟线）
上传时间： 2013-06-17
上传用户：haohaoxuexi
This unique guide to designing digital VLSI circuits takes a top-DOWN approach, reflecting the natureof the design process in industry. Starting with architecture design, the book explains the why andhow of digital design, using the physics that designers need to know, and no more.Covering system and component aspects, design verification, VHDL modelling, clocking, signalintegrity, layout, electricaloverstress, field-programmable logic, economic issues, and more, thescope of the book is singularly comprehensive.
标签： Integrated Digital Circuit Design
上传时间： 2013-11-04
上传用户：life840315
The STM32F10xxx microcontroller family embeds up to three advanced 12-bit ADCs (depending on the device) with a conversion time DOWN to 1 μs. A self-calibration feature is provided to enhance ADC accuracy versus environmental condition changes.
上传时间： 2014-12-23
上传用户：eastimage
This document provides practical, common guidelines for incorporating PCI Express interconnect layouts onto Printed Circuit Boards (PCB) ranging from 4-layer desktop baseboard designs to 10- layer or more server baseboard designs. Guidelines and constraints in this document are intended for use on both baseboard and add-in card PCB designs. This includes interconnects between PCI Express devices located on the same baseboard (chip-to-chip routing) and interconnects between a PCI Express device located “DOWN” on the baseboard and a device located “up” on an add-in card attached through a connector. This document is intended to cover all major components of the physical interconnect including design guidelines for the PCB traces, vias and AC coupling capacitors, as well as add-in card edge-finger and connector considerations. The intent of the guidelines and examples is to help ensure that good high-speed signal design practices are used and that the timing/jitter and loss/attenuation budgets can also be met from end-to-end across the PCI Express interconnect. However, while general physical guidelines and suggestions are given, they may not necessarily guarantee adequate performance of the interconnect for all layouts and implementations. Therefore, designers should consider modeling and simulation of the interconnect in order to ensure compliance to all applicable specifications. The document is composed of two main sections. The first section provides an overview of general topology and interconnect guidelines. The second section concentrates on physical layout constraints where bulleted items at the beginning of a topic highlight important constraints, while the narrative that follows offers additional insight.
上传时间： 2013-10-15
上传用户：busterman
LED Dimmingcontrol
标签： Step-DOWN Dimming Driver Using
上传时间： 2014-01-26
上传用户：watch100
1.2MHz 2A Synchronous Step-DOWN converter
上传时间： 2013-11-01
上传用户：qingzhuhu
Abstract: Some types of loads require more current during startup than when running. Other loads can be limited to a lower-powercurrent during startup but require a higher operating current. This article describes an application circuit that automatically adjusts apower circuit’s overcurrent protection level up or DOWN after startup is complete.
上传时间： 2013-10-22
上传用户：swaylong
The core voltages for FPGAs are moving lower as a resultof advances in the fabrication process. The newest FPGAfamily from Altera, the Stratix® II, now requires a corevoltage of 1.2V and the Stratix, Stratix GX, HardCopy®Stratix and CycloneTM families require a core voltage of1.5V. This article discusses how to power the core and I/Oof low voltage FPGAs using the latest step-DOWN switchmode controllers from Linear Technology Corporation.
上传时间： 2013-10-08
上传用户：wangfei22
The LTC®3414 offers a compact and efficient voltage regulatorsolution for point of load conversion in electronicsystems that require low output voltages (DOWN to 0.8V)from a 2.5V to 5V power bus. Internal power MOSFETswitches, with only 67mW on-resistance, allow theLTC3414 to deliver up to 4A of output current with efficiencyas high as 94%. The LTC3414 saves space by operatingwith switching frequencies as high as 4MHz, enabling theuse of tiny inductors and capacitors.
上传时间： 2014-01-02
上传用户：dongbaobao
