timing
共 131 篇文章
timing 相关的电子技术资料，包括技术文档、应用笔记、电路设计、代码示例等，共 131 篇文章，持续更新中。
VGA Timing Generator
基于Verilog实现的VGA时序控制模块，采用同步设计方法确保信号稳定性。支持标准VGA分辨率，适用于FPGA开发与显示接口调试。
xilinx_fpga_timing_constrain_guide
专为Xilinx FPGA设计优化的时序约束指南，涵盖时钟管理、路径分析与时序收敛技巧，工程师必备的实战参考手册。
Timing in the TTCAN Network
掌握TTCAN网络中的时序控制，确保数据传输的精确性和可靠性。这份资料深入解析了TTCAN协议下的时间同步机制，适用于需要高精度通信的应用场景。通过实际案例分析，帮助开发者快速理解并应用到项目中。
使用SpecctraQuest仿真时序问题
通常我们在计算时许问题时，一般重点遵循以下两个条件以保证足够的Timing Margin：
1. Tflightmax + Driver(Tcomax) + Skew + Jitter + Crosstalk + Receiver(Setup)< Clock Period
2. Tflightmin + Driver(Tcomin) - Receiver(Hold) - Skew - Cros
DM00074956
January 2013 Doc ID 024161 Rev 1 1/18
AN4235
Application note
I2C timing configuration tool
for STM32F3xxxx and STM32F0xxxxmicrocontrollers
EDID
EDID_Timing_Extension_Version_3详解
mpc8260ec
This document contains detailed information on power
considerations, DC/AC electrical characteristics, and AC
timing specifications for the .29 μm (HiP3) devices of the
PowerQUICC II family of comm
Virtex-II Platform FPGAs
Module 1:
Introduction and Overview
7 pages
• Summary of Features
• General Description
• Architecture
• Device/Package Combinations and Maximum I/O
• Ordering Examples
Module 2:
Functional D
HS-3282 DataSheet
The HS-3282 is a high performance CMOS bus interface
circuit that is intended to meet the requirements of ARINC
Specification 429, and similar encoded, time multiplexed
serial data protocols. This
Altera技术资料宝典系列(Timing)
Altera技术资料宝典系列(Timing)Altera公司的培训资料，很不错的。
fpga_timing.pdf
资料->【C】嵌入系统->【C2】IC设计与FPGA->【2】FPGA、CPLD->fpga_timing.pdf
Understanding I/O OutputTiming for Altera Devices
This application note describes the output timing parameters for Altera®<BR>devices, explains ho
NE558的应用说明
The 558 is a monolithic Quad Timer designed to be used in the<BR>timing range from a few microsecond
NE5561 NE5568的外部同步
<P>Synchronization of the 5561 can be accomplished by forcing the<BR>timing pin (Pin 5) above the 5.
使用XC9500XL时序模块
All XC9500XL CPLDs have a uniform architecture and an<BR>identical timing model, making them very ea
HSP50110和HSP50210及HSP43168实现多相位滤波
Polyphase resampling filters are often used for timing<BR>adjustments in bit synchronizer loops. The
介绍在XPLA3器件中执行在系统编程操作
With the possible exceptions of speed, deterministic timing, and low power, few things are as<BR>imp
SP6003 Synchronous Rectifier Driver
The essence of SP6003, the predictive timing<BR>circuitry, is based on several U.S. patented<BR>tech
sample_003
基于CPU的精确定时技术，实现并口通讯，从而完成数据采集，可以从16个通道中任意选择。-The precise timing based on CPU technology
FPGA Implementation Of Digital Timing Recovery In Software Radio Receiver
<P>FPGA Implementation Of Digital Timing Recovery In Software Radio Receiver:</P>