smclk
共 21 篇文章
smclk 相关的电子技术资料，包括技术文档、应用笔记、电路设计、代码示例等，共 21 篇文章，持续更新中。
MSP430F5438时钟测试引脚的使用例程
超低功耗单片机MSP430F5438的ACLK,MCLK,SMCLK测试引脚的使用例程
MSP430F5438外部晶振及系统时钟的配置
XT1高频模式的使用及ACLK、MCLK、SMCLK时钟源的选择。
Echo a received character, RX ISR used. Normal mode is LPM0. // USART1 RX interrupt triggers TX Ech
Echo a received character, RX ISR used. Normal mode is LPM0.
// USART1 RX interrupt triggers TX Echo.
// Baud rate divider with 1048576hz = 1048576/38400 = ~27.31 (01Bh|03h)
// ACLK = LFXT1 = 32768
msp430f5529 时钟配置25M
aclk 32khz smclk 25Mhz mclk 25mhz
//*** *** *** *** *** *** *** *** *** *** *** *** *** // MSP430x1xx Demo - Software Toggle P1.0 /
//*** *** *** *** *** *** *** *** *** *** *** *** ***
// MSP430x1xx Demo - Software Toggle P1.0
//
// Description Toggle P1.0 by xor ing P1.0 inside of a software loop.
// ACLK = n/a, MCLK = SMCL
MSP-FET430P140 Demo - Timer_B, PWM TB1-2, Up/Down Mode, DCO SMCLK
MSP-FET430P140 Demo - Timer_B, PWM TB1-2, Up/Down Mode, DCO SMCLK
MSP-FET430P140 Demo - Basic Clock, Output Buffered SMCLK, ACLK and MCLK
MSP-FET430P140 Demo - Basic Clock, Output Buffered SMCLK, ACLK and MCLK
MSP-FET430P440 Demo - Timer_A PWM TA1-2 upmode, DCO SMCLK
MSP-FET430P440 Demo - Timer_A PWM TA1-2 upmode, DCO SMCLK
MSP-FET430P440 Demo - WDT Toggle P5.1 Interval overflow ISR, DCO SMCLK
MSP-FET430P440 Demo - WDT Toggle P5.1 Interval overflow ISR, DCO SMCLK
VIP专区-嵌入式/单片机编程源码精选合集系列（60）
<b>VIP专区-嵌入式/单片机编程源码精选合集系列（60）</b><font color="red">资源包含以下内容：</font><br/>1. 16 * 16 的127个ascii码的点阵字库.<br/>2. ARM MP3解码源代码
实现MP3播放应用.<br/>3. 本文介基于CPLD和USB的多路温度数据采集系统.<br/>4. 89c51+sj1000 的发送例程
can2.0
Description: This program demonstrates a half-duplex 9600-baud UART using // Timer_A3 using no XTAL
Description: This program demonstrates a half-duplex 9600-baud UART using
// Timer_A3 using no XTAL and an external resistor for DCO ROSC. DCO used for
// TACLK UART baud generation. The program wil
//*** *** *** *** *** *** *** *** *** *** *** *** *** * // MSP-FET430x110 Demo - Software Toggle P1
//*** *** *** *** *** *** *** *** *** *** *** *** *** *
// MSP-FET430x110 Demo - Software Toggle P1.0
//
// Description: Toggle P1.0 by xor ing P1.0 inside of a software loop.
// ACLK = n/a, MCLK
D169 Demo - DMA0 Repeated Burst to-from RAM, Software Trigger Description A 32 byte block from 22
D169 Demo - DMA0 Repeated Burst to-from RAM, Software Trigger
Description A 32 byte block from 220h-240h is transfered to 240h-260h
using DMA0 in a burst block using software DMAREQ trigger.
Afte
MSP-FET430P410 Demo - Timer_A Toggle P5.1, CCR0 Contmode ISR, DCO SMCLK Description Toggle P5.1 u
MSP-FET430P410 Demo - Timer_A Toggle P5.1, CCR0 Contmode ISR, DCO SMCLK
Description Toggle P5.1 using using software and TA_0 ISR. Toggle rate is
set at 50000 DCO/SMCLK cycles. Default DCO freque
MSP-FET430P140 Demo - USART0, SPI Interface to HC165/164 Shift Registers Description: Demonstrate
MSP-FET430P140 Demo - USART0, SPI Interface to HC165/164 Shift Registers
Description: Demonstrate USART0 in two-way SPI mode. Data are read from
an HC165, and same data written back to the HC164.
MSP-FET430P440 Demo - BasicTimer Toggle P5.1 using ISR, 32kHz SMCLK
MSP-FET430P440 Demo - BasicTimer Toggle P5.1 using ISR, 32kHz SMCLK
MSP-FET430P440 Demo - BasicTimer Toggle P5.1 using ISR, DCO SMCLK
MSP-FET430P440 Demo - BasicTimer Toggle P5.1 using ISR, DCO SMCLK
MSP430F149串口行实验程序 //使用ADC12采集实验,将采集到数据送向PC.(序列单次采集,采用定时器A作为时钟源) //P3.4为发送,P3.5为接收 晶体使32768HZ/8MHZ.
MSP430F149串口行实验程序
//使用ADC12采集实验,将采集到数据送向PC.(序列单次采集,采用定时器A作为时钟源)
//P3.4为发送,P3.5为接收 晶体使32768HZ/8MHZ. 串行波特率B/S
//使用SMCLK作为波特率发器时,不能使用LPM2,LPM3!
MSP-FET430P120 Demo - Basic Clock, Output Buffered SMCLK, ACLK and MCLK/10
MSP-FET430P120 Demo - Basic Clock, Output Buffered SMCLK, ACLK and MCLK/10
宣读了一份tlc549 ADC的参考vcc使用软件SPI和存储8位数字代码在adcdata 。该tlc549采样
宣读了一份tlc549 ADC的参考vcc使用软件SPI和存储8位数字代码在adcdata 。该tlc549采样，在一个连续循环。如果adcdata > 0.5 * vcc ， p1.0设置，否则复位。aclk为N /甲mclk = smclk =预设会计处〜 800k vcc必须至少为3V为tlc549