skew

共 12 篇文章
skew 相关的电子技术资料,包括技术文档、应用笔记、电路设计、代码示例等,共 12 篇文章,持续更新中。

使用SpecctraQuest仿真时序问题

通常我们在计算时许问题时,一般重点遵循以下两个条件以保证足够的Timing Margin: 1. Tflightmax + Driver(Tcomax) + Skew + Jitter + Crosstalk + Receiver(Setup)< Clock Period 2. Tflightmin + Driver(Tcomin) - Receiver(Hold) - Skew - Cros

Skew definitions

Skew specifications are like any other AC<BR>electrical specification. The measurements<BR>are taken

在3.3V环境下使用CY7B991 CY7B9911和CY7B9910

The RoboClock&reg; family of low skew clock buffers includes six<BR>products listed in Table 1.

在3.3V工作电压下使用CY7B991,CY7B9911,CY7B9910可编程斜率时钟缓冲器

The RoboClock&reg; family of low skew clock buffers includes six<BR>products listed in Table 1.

Efficient skew estimation and correction algorithm for document images。一篇英文文献

Efficient skew estimation and correction algorithm for document images。一篇英文文献,内容新进。

A fast approach to the detection and correction of skew documentsIn this paper, a fast approach is p

A fast approach to the detection and correction of skew documentsIn this paper, a fast approach is proposed to detect and correct skew documents.

完整的jpeg encoder verilog code,DCT部分採用1991 IEEE transection paper,利用skew circular convolution來實現精簡電路

完整的jpeg encoder verilog code,DCT部分採用1991 IEEE transection paper,利用skew circular convolution來實現精簡電路

时钟分相技术应用

<p> 摘要: 介绍了时钟分相技术并讨论了时钟分相技术在高速数字电路设计中的作用。<br /> 关键词: 时钟分相技术; 应用<br /> 中图分类号: TN 79  文献标识码:A   文章编号: 025820934 (2000) 0620437203<br /> 时钟是高速数字电路设计的关键技术之一, 系统时钟的性能好坏, 直接影响了整个电路的<br /> 性能。尤其现代电子系统对性

Xilinx UltraScale:新一代架构满足您的新一代架构需求(EN)

<p>   <span style="color:#ff0000;"><strong>中文版详情浏览</strong></span>:<a href="http://www.elecfans.com/emb/fpga/20130715324029.html">http://www.elecfans.com/emb/fpga/20130715324029.html</a></p> <p>   X

Xilinx UltraScale:新一代架构满足您的新一代架构需求(EN)

<p>   <span style="color:#ff0000;"><strong>中文版详情浏览</strong></span>:<a href="http://www.elecfans.com/emb/fpga/20130715324029.html">http://www.elecfans.com/emb/fpga/20130715324029.html</a></p> <p>   X

使用时钟PLL的源同步系统时序分析

使用时钟PLL的源同步系统时序分析<BR>一)回顾源同步时序计算<BR>Setup Margin = Min Clock Etch Delay – Max Data Etch Delay – Max Delay Skew – Setup Time<BR>Hold Margin = Min Data Etch Delay – Max Clock Etch Delay + Min Delay Skew

SN65LBC170,SN75LBC170,pdf(TRIP

The SN65LBC170 and SN75LBC170 are<BR>monolithic integrated circuits designed for<BR>bidirectional data communication on multipoint<BR>bus-transmission lines. Potential applications<BR>include serial o