实现产生伪随机序列的部件 —— 线性反馈移位寄存器单元。 SFlog2为扩频因子的底数为2的对数值
实现产生伪随机序列的部件 —— 线性反馈移位寄存器单元。 SFlog2为扩频因子的底数为2的对数值，cycle为PN序列的周期，其值为2^SFlog2。initial_state为移位寄存器的初始状态...
cycle技术资料
📦 资源总数：77
💻 源代码：3906
🔌 电路图：1
📚 cycle全部资料 (77个)
The purpose of this document is to present how to use the Timer for the generation of a PWM signal t
The purpose of this document is to present how to use the Timer for the generation of a PWM signal t...
Top module name : SHIFTER (File name : SHIFTER.v) 2. Input pins: SHIFT [3:0], IN [15:0], SIGN, RIGH
Top module name : SHIFTER (File name : SHIFTER.v) 2. Input pins: SHIFT [3:0], IN [15:0], SIGN, RIGH...
Top module name : SHIFTER (File name : SHIFTER.v) 2. Input pins: SHIFT [3:0], IN [15:0], SIGN, RIGH
Top module name : SHIFTER (File name : SHIFTER.v) 2. Input pins: SHIFT [3:0], IN [15:0], SIGN, RIGH...
完成在tigersharc201平台上划分出多个heap的操作
完成在tigersharc201平台上划分出多个heap的操作，同时示例在多个heap之间切换时的方法，并做出各种内存下访问的cycle统计...
*** *** *** *** *** *** ***** ** Two wire/I2C Bus READ/WRITE Sample Routines of Microchip s ** 2
*** *** *** *** *** *** ***** ** Two wire/I2C Bus READ/WRITE Sample Routines of Microchip s ** 2...
It contains a vhdl description of the external bus interface unit for 68000 processor. currently onl
It contains a vhdl description of the external bus interface unit for 68000 processor. currently onl...
Edge Disjoint Cycles. You are given an input graph that is either directed or undirected. Write a pr
Edge Disjoint Cycles. You are given an input graph that is either directed or undirected. Write a pr...
蚁群算法经典TSP模型
蚁群算法经典TSP模型，ANT-CYCLE算法的实现。 使用了C++的STL库。 原是我毕设的一部分 现在贡献出来 。 PS:网上能得到的基本上不能直接运行 而我这个复制到vc++6.0的控...
This experiment uses the Blackfi n BF533/BF537 EZ-KIT to run a simple FIR fi lter on stereo channe
This experiment uses the Blackfi n BF533/BF537 EZ-KIT to run a simple FIR fi lter on stereo channe...