cplds
共 22 篇文章
cplds 相关的电子技术资料，包括技术文档、应用笔记、电路设计、代码示例等，共 22 篇文章，持续更新中。
高速XC9500XL的设计
CPLD design has advanced significantly beyond that of fast<BR>PAL design. Today's CPLDs must operate
使用XC9500XL时序模块
All XC9500XL CPLDs have a uniform architecture and an<BR>identical timing model, making them very ea
介绍CoolRunner系列XPLA3 CPLD器件的宏单元配置情况
Xilinx CoolRunner XPLA3 CPLDs provide designers with several useful configuration options<BR>for eac
高速XC9500XL的设计
CPLD design has advanced significantly beyond that of fast<BR>PAL design. Today's CPLDs must operate
使用XC9500XL时序模块
All XC9500XL CPLDs have a uniform architecture and an<BR>identical timing model, making them very ea
SM_GPIO_Altera_MAX_II_CPLD_Design_Example.zip
SMBus for GPIO Pin Expansion in MAX II CPLDs
SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example.zip
SPI to I2C Using MAX II CPLDs
Compact_Flash_Altera_MAX_II_CPLD_Design_Example.zip
CF+ Interface Using MAX II CPLDs
SPI_to_I2S_Altera_MAX_II_CPLD_Design_Example.zip
SPI to I2S Using MAX II CPLDs
Mobile_DRAM_Altera_MAX_II_CPLD_Design_Example.zip
Mobile SDRAM Interface Using MAX II CPLDs
synplify 201203sp2 软件下载
文件较大,存在百度网盘,下载文件中提供了链接和提取码。打开即可下载。synplify是专门针对FPGA和CPLD实现的逻辑综合工具,Synplicity的工具涵盖了可编程逻辑器件（FPGAs、PLDs和CPLDs）的综合，验证，调试，物理综合及原型验证等领域。
ATutorial: Architecture of FPGAs and CPLDs
ATutorial: Architecture of FPGAs and CPLDs
Power Management Solutions for Altera’s FPGAs and CPLDs
Power Management Solutions for Altera’s FPGAs and CPLDs，希望对大家有帮助！
Manchester Encoder - Decoder for Xilinx CPLDs Customer Pack
Manchester Encoder - Decoder for Xilinx CPLDs Customer Pack
XAPP105 - CPLD VHDL介绍
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This introduction covers the fundamentals of VHDL as applied to Complex ProgrammableLogic Devices (CPLDs). Specifically included are those design practices that translate soundlyto CPLDs, permi
xapp069 - 使用XC9500 JTAG边界扫描接口
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This application note explains the XC9500™/XL/XV Boundary Scan interface anddemonstrates the software available for programming and testing XC9500/XL/XV CPLDs. Anappendix summarizes the i
Analog Solutions for Altera FPGAs
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Designing withProgrammable Logicin an Analog WorldProgrammable logic devices revolutionizeddigital design over 25 years ago,promising designers a blank chip todesign literally any function and
Analog Solutions for Xilinx FPGAs
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Designing withProgrammable Logicin an Analog WorldProgrammable logic devicesrevolutionized digital design over 25years ago, promising designers a blankchip to design literally any functionand p
xapp069 - 使用XC9500 JTAG边界扫描接口
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This application note explains the XC9500™/XL/XV Boundary Scan interface anddemonstrates the software available for programming and testing XC9500/XL/XV CPLDs. Anappendix summarizes the i
Analog Solutions for Xilinx FPGAs
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Designing withProgrammable Logicin an Analog WorldProgrammable logic devicesrevolutionized digital design over 25years ago, promising designers a blankchip to design literally any functionand p