configured
共 59 篇文章
configured 相关的电子技术资料，包括技术文档、应用笔记、电路设计、代码示例等，共 59 篇文章，持续更新中。
This example describes how to use the ADC and DMA to transfer continuously converted data from ADC
This example describes how to use the ADC and DMA to transfer continuously
converted data from ADC to a data buffer.
The ADC is configured to converts continuously ADC channel14.
Each time an end
startup code has configured Timer0
startup code has configured Timer0
XAPP719 -利用USR_ACCESS寄存器实现PowerPC高速缓存配置
<div>
The Virtex™-4 user access register (USR_ACCESS_VIRTEX4) is a 32-bit register thatprovides direct access to bitstream data by the FPGA fabric. It is useful for loadingPowerPC™ 405 (P
using gpio of 2812 This program requires the DSP281x V1.00 header files. As supplied, this project
using gpio of 2812
This program requires the DSP281x V1.00 header files. As supplied, this project is configured for "boot to H0" operation.
This project is created using the Keil ARM CA Compiler. The Logic Analyzer built into the simula
This project is created using the Keil ARM CA Compiler.
The Logic Analyzer built into the simulator may be used to monitor and display any variable or peripheral I/O register. It is already config
startup code has configured Timer0
startup code has configured Timer0
Full support for extended regular expressions (those with intersection and complement); Support for
Full support for extended regular expressions (those with intersection and complement); Support for some kinds of cycles in grammar; DFA-based operation; Unicode support; C++ only, requires a modern c
CAN1.c and CAN2.c are a simple example of configuring a CAN network to transmit and receive data o
CAN1.c and CAN2.c are a simple example of configuring a CAN network to
transmit and receive data on a CAN network, and how to move information to
and from CAN RAM message objects. Each C8051F040-T
CAT93C46 器件数据手册
The CAT93C46 is a 1 kb Serial EEPROM memory device which is<BR>configured as either 64 registers of 16 bits (ORG pin at VCC) or 128<BR>registers of 8 bits (ORG pin at GND). Each register can be writte
XAPP719 -利用USR_ACCESS寄存器实现PowerPC高速缓存配置
<div>
The Virtex™-4 user access register (USR_ACCESS_VIRTEX4) is a 32-bit register thatprovides direct access to bitstream data by the FPGA fabric. It is useful for loadingPowerPC™ 405 (P
XAPP694-从配置PROM读取用户数据
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This application note describes how to retrieve user-defined data from Xilinx configurationPROMs (XC18V00 and Platform Flash devices) after the same PROM has configured theFPGA. The method to a
基于（英蓓特）STM32V100的看门狗程序
<P>This example shows how to update at regulate period the WWDG counter using the<BR>Early Wakeup interrupt (EWI).</P>
<P>The WWDG timeout is set to 262ms, refresh window set to 41h and the EWI is<BR>
带有SerDes接口的PLB千兆位级以太网MAC
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This application note describes a reference system which illustrates how to build an embeddedPowerPC® system using the Xilinx 1-Gigabit Ethernet Media Access Controller processor core.This
基于（英蓓特）STM32V100的串口程序
<P>This example provides a description of how to use the USART with hardware flow<BR>control and communicate with the Hyperterminal.<BR>First, the USART2 sends the TxBuffer to the hyperterminal
Virtex-5 GTP Transceiver Wizar
<P>The LogiCORE™ GTP Wizard automates the task of creating HDL wrappers to configure the high-speed serial GTP transceivers in Virtex™-5 LXT and SXT devices. The menu-driven interface allo
Virtex-5 GTP Transceiver Wizar
<P>The LogiCORE™ GTP Wizard automates the task of creating HDL wrappers to configure the high-speed serial GTP transceivers in Virtex™-5 LXT and SXT devices. The menu-driven interface allo
LTC6994参考设计及PCB布线规则
Demonstration circuit 1562A is an engineering tool<BR>to design and evaluate the LTC699X-X family of<BR>TimerBlox circuits. The center section of the board<BR>contains a pre-configured TimerBlox funct
XAPP694-从配置PROM读取用户数据
<div>
This application note describes how to retrieve user-defined data from Xilinx configurationPROMs (XC18V00 and Platform Flash devices) after the same PROM has configured theFPGA. The method to a
效率85％的12v转5v降压转换器
This application note describes how the NCP3063 can be configured as a buck controller to drive an e