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Tensilica 的查询结果
其他书籍 FFT implementation on tensilica
FFT implementation on tensilica
uCOS uCOS-II ports on Tensilica HiFi330 core.
uCOS-II ports on Tensilica HiFi330 core.
VHDL/FPGA/Verilog Tensilica开发平台实例
Tensilica开发平台实例,此工程项目文件可用Xtensa软件打开。
其他嵌入式/单片机内容 Tensilica平台应用实例
Tensilica平台应用实例,可用Xtensa软件打开。
微处理器开发 Tensilica应用平台实例
Tensilica应用平台实例,可用Xtensa软件打开。
微处理器开发 redboot在Tensilica平台上的源码
redboot在Tensilica平台上的源码
VHDL/FPGA/Verilog This is is a bridge IP core to interface the Tensilica PIF bus protocol with the OpenCores WishBone.
This is is a bridge IP core to interface the Tensilica PIF bus protocol with the OpenCores WishBone. It currently supports single-cycle as well as burst transfer operations. The core has been tested in a master-PIF slave-WB configuration.