Register
共 177 篇文章
Register 相关的电子技术资料，包括技术文档、应用笔记、电路设计、代码示例等，共 177 篇文章，持续更新中。
AT89C2051驱动步进电机的电路和源码
AT89C2051驱动步进电机的电路和源码:AT89C2051驱动步进电机的电路和源码 程序:<BR>stepper.c stepper.hex<BR>/* * STEPPER.C * sweeping stepper's rotor cw and cww 400 steps * Copyright (c) 1999 by W.Sirichote */<BR>＃i nclude c:\mc5151
CAT93C46 器件数据手册
The CAT93C46 is a 1 kb Serial EEPROM memory device which is<BR>configured as either 64 registers of 16 bits (ORG pin at VCC) or 128<BR>registers of 8 bits (ORG pin at GND). Each register can be writte
C51使用手册
<P><STRONG>C51使用手册 .pdf</STRONG></P>
<P>第二节内存区域(Memory Areas)<BR>1. Pragram Area<BR>由Code 说明可有多达64kBytes 的程序存储器<BR>2. Internal Data Memory:<BR>内部数据存储器可用以下关键字说明<BR>data 直接寻址区为内部RAM 的低128 字节00H 7FH<BR>i
PCA9546A 4 channel I2C bus swi
The PCA9546A is a quad bidirectional translating switch controlled via the I2C-bus. The<BR>SCL/SDA upstream pair fans out to four downstream pairs, or channels. Any individual<BR>SCx/SDx channel or co
PCA9555 16bit I2C-bus and SMBu
<P>The PCA9555 is a 24-pin CMOS device that provides 16 bits of General Purpose parallel<BR>Input/Output (GPIO) expansion for I2C-bus/SMBus applications and was developed to<BR>enhance the NXP Semicon
XAPP719 -利用USR_ACCESS寄存器实现PowerPC高速缓存配置
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The Virtex™-4 user access register (USR_ACCESS_VIRTEX4) is a 32-bit register thatprovides direct access to bitstream data by the FPGA fabric. It is useful for loadingPowerPC™ 405 (P
基于CORDIC算法的高速ODDFS电路设计
<span id="LbZY">为了满足现代高速通信中频率快速转换的需求，基于坐标旋转数字计算（CORDIC，Coordinate Rotation Digital Computer）算法完成正交直接数字频率合成（ODDFS，Orthogonal Direct Digital Frequency Synthesizer）电路设计方案。采用MATLAB和Xilinx System Generator
8-bit IC and SMBus IO Port wit
The CAT9534 is an 8-bit parallel input/output portexpander for I²C and SMBus compatible applications.These I/O expanders provide a simple solution inapplications where additional I/Os are needed:
51单片机驱动步进电机(含电路图和C语言源程序代码)
<P>51单片机驱动步进电机(含电路图和源程序代码）</P>
<P>源程序:<BR>stepper.c <BR>stepper.hex <BR>/* <BR>* STEPPER.C <BR>* sweeping stepper's rotor cw and cww 400 steps <BR>* Copyright (c) 1999 by W.Sirichote <BR>*/ <BR>＃i ncl
keil使用笔记
keil 使用笔记:在Memory窗口上输入address_type:address才能看到正确地址的变量debug～perfermance analyzer加入要察看的模块名称，然后view～perfermance analyzer window 可以察看各个模块运行时间①Display address_type:address B:Bit address C:Code Memory Bx:Co
MAXQUSBJTAGOW评估板软件
MAXQUSBJTAGOW评估板软件:关键特性 Easily Load and Debug Code Interface Provides In-Application Debugging Features Step-by-Step Execution Tracing Breakpointing by Code Address, Data Memory Address, or Register A
MPLAB C30用户指南(英文)
<P><STRONG>MPLAB C30用户指南(英文)</STRONG></P>
<P><STRONG>HIGHLIGHTS</STRONG><BR>The information covered in this chapter is as follows:<BR>• About this Guide<BR>• Recommended Reading<BR>•
PCA9548A 8 channel I2C bus swi
The PCA9548A is an octal bidirectional translating switch controlled via the I2C-bus. The<BR>SCL/SDA upstream pair fans out to eight downstream pairs, or channels. Any individual<BR>SCx/SDx channel or
PCA954X家庭的I C SMBus多路复用器与开关
<P>The Philips family of Multiplexers and Switches consists of bi-directional translating switches controlled via the I2C or SMBus to fan out an upstream SCL/SDA pair to 2, 4 or 8 downstream channels
C51中的关键字及用途说明
C51 中的关键字<BR>关键字 用途 说明<BR>auto 存储种类说明 用以说明局部变量，缺省值为此<BR>break 程序语句 退出最内层循环<BR>case 程序语句 Switch 语句中的选择项<BR>char 数据类型说明 单字节整型数或字符型数据<BR>const 存储类型说明 在程序执行过程中不可更改的常量值<BR>continue 程序语句 转向下一次循环<BR>default
JPEG2000算术编码的研究与FPGA实现
JPEG2000是由ISO/ITU-T组织下的IEC JTC1/SC29/WG1小组制定的下一代静止图像压缩标准.与JPEG(Joint Photographic Experts Group)相比,JPEG2000能够提供更好的数据压缩比,并且提供了一些JPEG所不具有的功能[1].JPEG2000具有的多种特性使得它具有广泛的应用前景.但是,JPEG2000是一个复杂编码系统,目前为止的软件实现
74LS164.pdf
英文描述： 8-Bit Serial-Input/Parallel-Output Shift Register
中文描述： 8位Serial-Input/Parallel-Output移位寄存器