Limited
共 111 篇文章
Limited 相关的电子技术资料，包括技术文档、应用笔记、电路设计、代码示例等，共 111 篇文章，持续更新中。
基于单DSP的VoIP模拟电话适配器研究与实现
<P>基于单DSP的VoIP模拟电话适配器研究与实现:提出和实现了一种新颖的基于单个通用数字信号处理器(DSP)的VoIP模拟电话适配器方案。DSP的I/O和存储资源非常有限，通常适于运算密集型应用，不适宜控制密集型应用[5]。该系统高效利用单DSP的I/O和片内外存储器资源，采用μC/OS-II嵌入式实时操作系统，支持SIP和TCP-UDP/IP协议，通过LAN或者宽带接入，使普通电话机成为In
为您的FPGA选择合适的电源
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Abstract: There are many things to consider when designing a power supply for a field-programmablegate array (FPGA). These include (but are not limited to) the high number of voltage rails, and
Virtex-6 FPGA PCB设计手册
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Xilinx is disclosing this user guide, manual, release note, and/or specification (the "Documentation") to you solely for use in the developmentof designs to operate with Xilinx hardwa
为您的FPGA选择合适的电源
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Abstract: There are many things to consider when designing a power supply for a field-programmablegate array (FPGA). These include (but are not limited to) the high number of voltage rails, and
基于单片机系统的(24,16)循环码编码、译码方案
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在理论分析循环码编码和译码基本原理的基础上，提出了基于单片机系统的(24，16)循环码软件实现编码、译码的方案。仿真结果表明(24，16)循环码能有效地克服来自通讯信道的干扰，保证数据通信的可靠及系统的稳定，使误码率大幅度降低。本论文对(24，16)循环码的研究结果表明，可以有效地降低错误概率和提高系统的吞吐量，实现纠错仅需要在接收端增加有限的存储空间和计算复杂度，具有一定的实用价值
FET430PIF自制资料
<P>The MSP-FET430PIF is a Parallel Port interface (does not include target board) that is used to program and debug MSP430 FET tools and test boards through the JTAG interface. This interface is inclu
如何保护集成FET的电源开关
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Abstract: Some types of loads require more current during startup than when running. Other loads can be limited to a lower-powercurrent during startup but require a higher operating current. Th
CPLD库指南
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Xilinx is disclosing this user guide, manual, release note, and/or specification (the “Documentation”) to you<br />
solely for use in the development of designs to operate with Xilin
LTC1325电池管理IC的使用
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For a variety of reasons, it is desirable to charge batteriesas rapidly as possible. At the same time, overchargingmust be limited to prolong battery life. Such limitation ofove
Adding 32 KB of Serial SRAM to
<P>Although Stellaris microcontrollers have generous internal SRAM capabilities, certain applicationsmay have data storage requirements that exceed the 8 KB limit of the Stellaris LM3S8xx seriesdevice
关于FPGA流水线设计的论文
关于FPGA流水线设计的论文\r\nThis work investigates the use of very deep pipelines for\r\nimplementing circuits in FPGAs, where each pipeline\r\nstage is limited to a single FPGA logic element (LE). The\r\narchi