Errors
共 96 篇文章
Errors 相关的电子技术资料，包括技术文档、应用笔记、电路设计、代码示例等，共 96 篇文章，持续更新中。
The idea behind differential GPS is to remove as much errors as possible from the range measurements
The idea behind differential GPS is to remove as much errors as possible from the range measurements by establishing these errors at a reference site. In its most simple setup, a GPS receiver is locat
While every precaution has been taken in the preparation of this book, the publisher assumes no re
While every precaution has been taken in the preparation of this book, the publisher assumes no
responsibility for errors or omissions, or for damages resulting from the use of the information
con
orcad无法输出网表问题解决方法
ORCAD在使用的时候总会出现这样或那样的问题…<BR>但下这个问题比较奇怪…在ORCAD中无法输出网表…<BR>弹出下面的错误….这种问题很是奇怪…<BR>Netlist Format: tango.dll<BR>Design Name: D:\EDA_PROJECT\PROTEL99SE\YK\SV3200\MAIN.DSN<BR>ERROR [NET0021] Cannot get part
高速电路传输线效应分析与处理
随着系统设计复杂性和集成度的大规模提高，电子系统设计师们正在从事100MHZ以上的电路设计，总线的工作频率也已经达到或者超过50MHZ，有一大部分甚至超过100MHZ。目前约80% 的设计的时钟频率超过50MHz，将近50% 以上的设计主频超过120MHz，有20%甚至超过500M。<BR>当系统工作在50MHz时，将产生传输线效应和信号的完整性问题；而当系统时钟达到120MHz时，除非使用高速电
基准电压的温度漂移研究应用笔记
<div>
Abstract: A perfect voltage reference produces a stable voltage independent of any external factors. Real-world voltagereferences, of course, are subject to errors caused by many external facto
高速电路传输线效应分析与处理
随着系统设计复杂性和集成度的大规模提高，电子系统设计师们正在从事100MHZ以上的电路设计，总线的工作频率也已经达到或者超过50MHZ，有一大部分甚至超过100MHZ。目前约80% 的设计的时钟频率超过50MHz，将近50% 以上的设计主频超过120MHz，有20%甚至超过500M。<BR>当系统工作在50MHz时，将产生传输线效应和信号的完整性问题；而当系统时钟达到120MHz时，除非使用高速电
WP276 -可编程的开发和测试
<div>
We all know the benefits of using FieldProgrammable Gate Arrays (FPGAs): no NRE, nominimum order quantities, and faster time-tomarket.In an ideal world, designs would never needto be changed be
PCI ExpressTM Architecture
<P>PCI ExpressTM Architecture</P>
<P>Add-in Card Compliance Checklist for the PCI Express Base 1.0a Specification<BR>The PCI Special Interest Group disclaims all warranties and liability for the use o
orcad无法输出网表问题解决方法
ORCAD在使用的时候总会出现这样或那样的问题…<BR>但下这个问题比较奇怪…在ORCAD中无法输出网表…<BR>弹出下面的错误….这种问题很是奇怪…<BR>Netlist Format: tango.dll<BR>Design Name: D:\EDA_PROJECT\PROTEL99SE\YK\SV3200\MAIN.DSN<BR>ERROR [NET0021] Cannot get part
PCI总线的应用
The PCI Special Interest Group disclaims all warranties and liability for the use of this document and the information contained herein and assumes no responsibility for any errors that may appear in
电源调整与虚拟地
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Abstract: Rail splitting is creating an artificial virtual ground as a reference voltage. It is used to set the signalto match the op amp's "sweet spot." An op amp has the most li
CPLD库指南
<p>
Xilinx is disclosing this user guide, manual, release note, and/or specification (the “Documentation”) to you<br />
solely for use in the development of designs to operate with Xilin
3.3v看门狗芯片
<P>The STWD100 watchdog timer circuits are self-contained devices which prevent system<BR>failures that are caused by certain types of hardware errors (non-responding peripherals,<BR>bus contention, e
SUNPLUSIT编程工具Q-Writer使用说明书
Important Notice <BR>SUNPLUS INNOVATION TECHNOLOGY INC. reserves the right to change this documentation without prior <BR>notice. Information provided by SUNPLUS INNOVATION TECHNOLOGY INC.
CF卡技术资料
The information in this specification is subject to change without notice.<BR>Use of this specification for product design requires an executed license agreement from the CompactFlash<BR>Association.<
嵌入式实时操作系统MicroCOS_II光盘内容.rar
MicroC/OS-II
The Real-Time Kernel
Second Edition
By Jean J. Labrosse
CMP Books, CMP Media LLC
Copyright 2002 by CMP Books
ISBN 1-57820-103-9
CMP Books
CMP Media LLC
1601 West 23rd Stree