Demodulator
共 13 篇文章
Demodulator 相关的电子技术资料，包括技术文档、应用笔记、电路设计、代码示例等，共 13 篇文章，持续更新中。
基于串口的信号源与解调器微机控制系统The Computer Control System for Singal Generator and Demodulator Based onSerialPor
<P>采用通用微机，基于串口，实现对遥感卫星地面接收系统中二次变频本振信号源和卫星下行数据高速解调器的控制，替代原有的人工设置的模式，实现了对信号源和解调器可靠、灵活、高效的控制。<BR>关键字：信号
ADC模数转换器件Altium Designer AD原理图库元件库
<p>ADC模数转换器件Altium Designer AD原理图库元件库</p><p>SV text has been written to file : 4.4 - ADC模数转换器件.csv</p><p><br/></p><p>Library Component Count : 29</p><p><br/></p><p>Name &nbs
QAM 4 Modulator and Demodulator based on ETSI TETRA Standard
QAM 4 Modulator and Demodulator based on ETSI TETRA Standard
Process a binary data stream using a communication system that consists of a baseband modulator, c
Process a binary data stream using a communication system that
consists of a baseband modulator, channel, and demodulator.
Compute the system s bit error rate (BER). Also, display
the transmitte
This paper investigates the design of joint frequency offset and carrier phase estimation of a mult
This paper investigates the design of joint frequency
offset and carrier phase estimation of a multi-frequency time division
multiple access (MF-TDMA) demodulator that is applied to
a digital video
receiver matlab demodulator
receiver matlab demodulator
This packet is a IS-95 baseband simulation for 1 data channel of 9.6 KBps rate. The simulation is
This packet is a IS-95 baseband simulation for 1 data channel of 9.6 KBps rate.
The simulation is written for static channel and AWGN noise. The packet include:
1) Packet Builder (Viterbi Encoding
This packet is a IS-95 baseband simulation for 1 data channel of 9.6 KBps rate. The simulation is wr
This packet is a IS-95 baseband simulation for 1 data channel of 9.6 KBps rate. The simulation is written for static channel and AWGN noise.
The packet include:
1) Packet Builder (Viterbi Encoding
TAD10023 Demodulator From NXP.CU1216 is tuner.
TAD10023 Demodulator From NXP.CU1216 is tuner.
基于CPLD的QDPSK调制解调电路设计
为了在CDMA系统中更好地应用QDPSK数字调制方式，在分析四相相对移相（QDPSK)信号调制解调原理的基础上，设计了一种QDPSK调制解调电路，它包括串并转换、差分编码、四相载波产生和选相、相干解调、差分译码和并串转换电路。在MAX+PLUSⅡ软件平台上，进行了编译和波形仿真。综合后下载到复杂可编程逻辑器件EPM7128SLC84-15中，测试结果表明，调制电路能正确选相，解调电路输出数据与QD
his packet is a IS-95 baseband simulation for 1 data channel of 9.6 KBps rate. The simulation is w
his packet is a IS-95 baseband simulation for 1 data channel of 9.6 KBps rate.
The simulation is written for static channel and AWGN noise. The packet include:
1) Packet Builder (Viterbi Encoding,
基于CPLD的QDPSK调制解调电路设计
为了在CDMA系统中更好地应用QDPSK数字调制方式，在分析四相相对移相（QDPSK)信号调制解调原理的基础上，设计了一种QDPSK调制解调电路，它包括串并转换、差分编码、四相载波产生和选相、相干解调、差分译码和并串转换电路。在MAX+PLUSⅡ软件平台上，进行了编译和波形仿真。综合后下载到复杂可编程逻辑器件EPM7128SLC84-15中，测试结果表明，调制电路能正确选相，解调电路输出数据与QD
基于HITAG读写芯片HTRC110的读写设备设计
<p>
Designing read/write device (RWD) units for industrial RF-Identification<br />
applications is strongly facilitated by the NXP Semiconductors HITAG<br />
Reader Chip HTRC110. All needed functio