Actel FPGA A3P600最小系统原理图

<img src="/uploads/pic/8b/28b/c4389ade2e8459a940098d90319e628b-1.png

完整的数字频率计程序 完整的数字频率计程序

<img src="/uploads/pic/68/568/6f952be80af8b70d35716982e37a4568-1.

Video信号pal制转vga输出，fpga Verilong语言编写

<img src="/uploads/pic/45/f45/f506658caca3eed0b571ad94ccca4f45

UART FPGA实现过程文档说明，及VERILOG HDL代码

<img src="/uploads/pic/c9/fc9/06cd9bcc006dad9c3ddd6f27c2171fc9

FPGA设计的SDRAM控制器，有仿真代码，已通过验证

<img src="/uploads/pic/52/152/1d9371aff5b58e8c6665356fda343152-1

基于xilinx virtex5的猜数游戏 基于xilinx virtex5的猜数游戏

<img src="/uploads/pic/ff/bff/efd68b29f45b973fe81b17605ff21bff

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用verilog实现的串口收发数据程序，已经调试通过

<img src="/uploads/pic/a5/ca5/79a43b53ea717f6c119743ccaa95dca5-1.

基于FPGA的蓝牙数据采集系统 基于FPGA的蓝牙数据采集系统

<img src="/uploads/pic/a0/ba0/3c11b2f6f288cbd20cec85a92fa0cba0

DE2-70FPGA开发板的音频处理程序

<img src="/uploads/pic/2e/12e/9880a59272b910e75b667e191301912e-1.png" alt

xilinx官方推出的基于xilinx FPGA的PCIE设计的教程

<img src="/uploads/pic/11/711/ebe18ab12e9bc482abcfea51f65be711

基于altera fpga 的单口ram ip核的应用实例

<img src="/uploads/pic/f0/4f0/fb58811336e25bcefac70bf96ae994f0

基于VHDL的时钟设计（de2开发平台） 基于VHDL的时钟设计（de2开发平台）

<img src="/uploads/pic/40/140/1473bdcf646691b6bd7daeaabc237140

Xilinx Spartan6开发板原理图及PCB图

<img src="/uploads/pic/fe/afe/17fdd033cc3dd40c32ecc5084654aafe-1.

XILINX CPLD_FPGA 并口下载线的原理图

<img src="/uploads/pic/96/f96/ecd30c0fb2521914fd97b4c47a307f96-1.

fpga axi测试程序,可测试符合axi协议的ip核

<img src="/uploads/pic/69/c69/5466403bb9303e4f9cbea97250a6ec69-1

高速ADC及DAC接口的参考设计

<img src="/uploads/pic/c9/1c9/c6a4ff491cc0fb4ef15b123d1f2c81c9-1.png" alt="

FPGA驱动OV7620程序代码 FPGA驱动OV7620程序代码

<img src="/uploads/pic/18/a18/10d3489e8b763fade50ef51f46f02a18

视频采集输出实例，FPGA视频采集和输出

<img src="/uploads/pic/6d/d6d/87ba2026bbf42d1ea8a23c50029d9d6d-1.png" alt

ALTERA公司的CYCLONE FPGA开发板详细原理图

<img src="/uploads/pic/fd/1fd/7185213cf6477d88d184fcfe6e0301fd