中文版详情浏览：http://www.elecfans.com/emb/fpga/20130715324029.html Xilinx UltraScale:The Next-Generation Architecture for Your Next-Generation Architecture The Xilinx® UltraScale™ architecture delivers unprecedented levels of integration and capability with ASIC-class system- level performance for the most demanding applications. The UltraScale architecture is the industr y's f irst application of leading-edge ASIC architectural enhancements in an All Programmable architecture that scales from 20 nm planar through 16 nm FinFET technologies and beyond, in addition to scaling from monolithic through 3D ICs. Through analytical co-optimization with the X ilinx V ivado® Design Suite, the UltraScale architecture provides massive routing capacity while intelligently resolving typical bottlenecks in ways never before possible. This design synergy achieves greater than 90% utilization with no performance degradation. Some of the UltraScale architecture breakthroughs include: • Strategic placement (virtually anywhere on the die) of ASIC-like system clocks, reducing clock skew by up to 50% • Latency-producing pipelining is virtually unnecessary in systems with massively parallel bus architecture, increasing system speed and capability • Potential timing-closure problems and interconnect bottlenecks are eliminated, even in systems requiring 90% or more resource utilization • 3D IC integration makes it possible to build larger devices one process generation ahead of the current industr y standard • Greatly increased system performance, including multi-gigabit serial transceivers, I/O, and memor y bandwidth is available within even smaller system power budgets • Greatly enhanced DSP and packet handling The Xilinx UltraScale architecture opens up whole new dimensions for designers of ultra-high-capacity solutions.
标签： UltraScale Xilinx 架构
上传时间： 2013-11-13
上传用户：瓦力瓦力hong
The information in this specification is subject to change without notice.Use of this specification for product design requires an executed license agreement from the CompactFlashAssociation.The CompactFlash Association shall not be liable for technical or editorial errors or omissions contained herein; norfor incidental or consequential damages resulting from the furnishing, performance, or use of this material.All parts of the CompactFlash Specification are protected by copyright law and all rights are reserved. Thisdocumentation may not, in whole or in part, be copied, photocopied, reproduced, translated, or reduced to anyelectronic medium or machine readable form without prior consent, in writing, from the CompactFlash Association.The CFA logo is a trademark of the CompactFlash Association.Product names mentioned herein are for identification purposes only and may be trademarks and/or registeredtrademarks of their respective companies.© 1998-99, CompactFlash Association. All rights reserved.
标签： 技术资料
上传时间： 2013-10-07
上传用户：stewart·
This is the second half of our Transistor Circuits e-book. It contains a further 100 circuits, with many of them containing one or more Integrated Circuits (ICs).It's amazing what you can do with transistors but when Integrated Circuits came along, the whole field of electronics exploded.
上传时间： 2013-11-08
上传用户：603100257
中文版详情浏览：http://www.elecfans.com/emb/fpga/20130715324029.html Xilinx UltraScale:The Next-Generation Architecture for Your Next-Generation Architecture The Xilinx® UltraScale™ architecture delivers unprecedented levels of integration and capability with ASIC-class system- level performance for the most demanding applications. The UltraScale architecture is the industr y's f irst application of leading-edge ASIC architectural enhancements in an All Programmable architecture that scales from 20 nm planar through 16 nm FinFET technologies and beyond, in addition to scaling from monolithic through 3D ICs. Through analytical co-optimization with the X ilinx V ivado® Design Suite, the UltraScale architecture provides massive routing capacity while intelligently resolving typical bottlenecks in ways never before possible. This design synergy achieves greater than 90% utilization with no performance degradation. Some of the UltraScale architecture breakthroughs include: • Strategic placement (virtually anywhere on the die) of ASIC-like system clocks, reducing clock skew by up to 50% • Latency-producing pipelining is virtually unnecessary in systems with massively parallel bus architecture, increasing system speed and capability • Potential timing-closure problems and interconnect bottlenecks are eliminated, even in systems requiring 90% or more resource utilization • 3D IC integration makes it possible to build larger devices one process generation ahead of the current industr y standard • Greatly increased system performance, including multi-gigabit serial transceivers, I/O, and memor y bandwidth is available within even smaller system power budgets • Greatly enhanced DSP and packet handling The Xilinx UltraScale architecture opens up whole new dimensions for designers of ultra-high-capacity solutions.
标签： UltraScale Xilinx 架构
上传时间： 2013-11-21
上传用户：wxqman
Although there has been a lot of AVL tree libraries available now, nearly all of them are meant to work in the random access memory(RAM). Some of them do provide some mechanism for dumping the whole tree into a file and loading it back to the memory in order to make data in that tree persistent. It serves well when there s just small amount of data. When the tree is somewhat bigger, the dumping/loading process could take a lengthy time and makes your mission-critical program less efficient. How about an AVL tree that can directly use the disk for data storage ? If there s something like that, we won t need to read through the whole tree in order to pick up just a little bit imformation(a node), but read only the sectors that are neccssary for locating a certain node and the sectors in which that node lies. This is my initial motivation for writing a storage-media independent AVL Tree. However, as you step forth, you would find that it not only works fine with disks but also fine with memorys, too.
标签： available libraries Although nearly
上传时间： 2014-01-22
上传用户：zhoujunzhen
county, random population coordinates were generated using the complete spatial randomness (CSR) function in S-PLUS. Then, the background information was attached to each individual county based on the county?s distribution for the class of interest. Finally, all counties were merged into a single dataset that describes the whole state
标签： coordinates population randomness generated
上传时间： 2014-01-17
上传用户：hn891122
Following is a repost of the public domain make that I posted to net.sources a couple of months ago. I have fixed a few bugs, and added some more features, and the resulting changes amounted to about as much text as the whole program (hence the repost).一个编译器C代码，详见REDME。
标签： Following sources domain couple
上传时间： 2015-08-31
上传用户：manlian
This tutorial attempts to get you started developing with the Win32 API as quickly and clearly as possible. It is meant to be read as a whole, so please read it from beginning to end before asking questions... most of them will probably be answered. Each section builds on the sections before it. I have also added some solutions to common errors in Appendix A. If you ask me a question that is answered on this page, you will look very silly.
标签： developing tutorial attempts clearly
上传时间： 2015-09-28
上传用户：wanqunsheng
VCLSkin™ is a component to create skinnable user interface for Delphi/C++Builder application, It is easy to use, just put on component on mainform, Vclskin will skin whole application without source code modification.
标签： application component interface skinnable
上传时间： 2014-01-25
上传用户：gxmm
A system simulation environment in Matlab/Simulink of RFID is constructed in this paper. Special attention is emphasized on the analog/RF circuit.Negative effects are concerned in the system model,such as phase noise of the local oscillator,TX-RX coupling,reflection of the environment, AWGN noise,DC offset,I/Q mismatch,etc.Performance of the whole system can be evaluated by changing the coding method,parameters of building blocks,and operation distance.Finally,some simulation results are presented in this paper.
标签： environment constructed simulation Simulink
上传时间： 2014-01-09
上传用户：zhangliming420
