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  • 16点FFT VHDL源程序

    16点FFT VHDL源程序,The xFFT16 fast Fourier transform (FFT) Core computes a 16-point complex FFT. The input data is a vector of 16 complex values represented as 16-bit 2’s complement numbers – 16-bits for each of the real and imaginary component of a datum.

    标签: VHDL FFT 源程序

    上传时间: 2013-12-20

    上传用户:yph853211

  • 实现基本的购物车功能。 eclipse+sqlserver2005 1.主要强调了购物车的业务逻辑。 2

    实现基本的购物车功能。 eclipse+sqlserver2005 1.主要强调了购物车的业务逻辑。 2,利用javabean封装。比较适合jsp初学者。 3.简洁实用。可以在此基础上开发更加复杂功能的购物网站。 数据库建立 create database shop_db go use shop_db go create table t_sp ( s_id int identity(1,1) primary key, s_name varchar(20) not null, s_price money not null ) go insert into t_sp values( IBM笔记本电脑 , 19999 ) insert into t_sp values( Hp商务笔记本电脑 , 8666 ) insert into t_sp values( 精通JSP技术 , 236 ) insert into t_sp values( ASP.NET高级应用 , 156 ) insert into t_sp values( J2EE高级开发 , 126 ) insert into t_sp values( 华硕笔记本电脑 , 6789 ) go select * from t_sp go

    标签: sqlserver eclipse 2005 逻辑

    上传时间: 2013-12-19

    上传用户:netwolf

  • ResOrg 图形化管理Vc项目的资源ID的工具的源代码。 ResOrg - Manage and Renumber Resource Symbol IDs Introduction The

    ResOrg 图形化管理Vc项目的资源ID的工具的源代码。 ResOrg - Manage and Renumber Resource Symbol IDs Introduction The Resource ID Organiser (ResOrg for short) is an Add-in for Visual C++ designed to help overcome one of the most annoying (and unnecessary) chores of developing/maintaining Windows applications - maintaining resource symbol ID values.

    标签: ResOrg Introduction Renumber Resource

    上传时间: 2013-12-25

    上传用户:dsgkjgkjg

  • *** *** *** *** *** *** ***** ** Two wire/I2C Bus READ/WRITE Sample Routines of Microchip s ** 2

    *** *** *** *** *** *** ***** ** Two wire/I2C Bus READ/WRITE Sample Routines of Microchip s ** 24Cxx / 85Cxx serial CMOS EEPROM interfacing to a ** PIC16C54 8-bit CMOS single chip microcomputer ** Revsied Version 2.0 (4/2/92). ** ** Part use = PIC16C54-XT/JW ** Note: 1) All timings are based on a reference crystal frequency of 2MHz ** which is equivalent to an instruction cycle time of 2 usec. ** 2) Address and literal values are read in octal unless otherwise ** specified.

    标签: Microchip Routines Sample WRITE

    上传时间: 2013-12-27

    上传用户:ljmwh2000

  • It has been suggested1 that an appropriate figure of merit for a low probability of intercept and d

    It has been suggested1 that an appropriate figure of merit for a low probability of intercept and detection (LPI/D) waveform is the quantity “Range x Bandwidth / Joule”. That is, the further the range, the wider the bandwidth and the less amount of energy used to achieve these values, the more covert is the resultant communications system.

    标签: appropriate probability suggested1 intercept

    上传时间: 2017-01-03

    上传用户:kr770906

  • 该工具用Delphi7写的

    该工具用Delphi7写的,可帮助我们生成一些插入语句。 例如: 现要向一台机(P2)的数据库(以HR为例)插入另一台机(P1)的HR_New_Info记录,可如下操作: 1.输入P1的IP,用户名,密码。数据库输入“HR” 2.在查询语句输入 select Title,Content,TypeName,Flag,DateAndTime from HR_New_Info 3.在插入语句输入 insert into HR_New_Info(Title,Content,TypeName,Flag,DateAndTime) 4.点击生成语句,可生成如下语句: insert into HR_New_Info(Title,Content,TypeName,Flag,DateAndTime) values( 政府招聘网上报名系统投入使用 , , 新闻资信 ,True, 2008-9-30 ) insert into HR_New_Info(Title,Content,TypeName,Flag,DateAndTime) values( 防洪防汛工作顺利完成 , , 新闻资信 ,True, 2008-9-15 ) 注,语句暂时只能保存为.sql文件

    标签: Delphi7

    上传时间: 2017-01-21

    上传用户:zxc23456789

  • GTKores is a simple color picking tool, written in GTK+/C, and runs under Linux/X11. It makes easier

    GTKores is a simple color picking tool, written in GTK+/C, and runs under Linux/X11. It makes easier tasks where you need hex color values, such writing CSS and HTML pages.

    标签: GTKores picking written easier

    上传时间: 2014-08-18

    上传用户:123啊

  • Verilog Overview n Basic Structure of a Verilog Model n Components of a Verilog Module – Ports –

    Verilog Overview n Basic Structure of a Verilog Model n Components of a Verilog Module – Ports – Data Types – Assigning values and Numbers – Operators – Behavioral Modeling • Continuous Assignments • Procedural Blocks – Structural Modeling n Summary: Verilog Environment

    标签: Verilog Components Structure Overview

    上传时间: 2017-02-17

    上传用户:xinyuzhiqiwuwu

  • BugNET is an issue tracking and project issue management solution built using the ASP.NET web applic

    BugNET is an issue tracking and project issue management solution built using the ASP.NET web application framework. Email notifications, reporting and per project configuration of fields and values allows efficient management of bugs, feature requests, and other issues for projects of any scale.

    标签: issue management tracking solution

    上传时间: 2014-08-10

    上传用户:181992417

  • Auctions are among the oldest economic institutions in place. They have been used since antiquity to

    Auctions are among the oldest economic institutions in place. They have been used since antiquity to sell a wide variety of goods, and their basic form has remained unchanged. In this dissertation, we explore the efficiency of common auctions when values are interdependent- the value to a particular bidder may depend on information available only to others-and asymmetric. In this setting, it is well known that sealed-bid auctions do not achieve efficient allocations in general since they do not allow the information held by different bidders to be shared.

    标签: institutions antiquity Auctions economic

    上传时间: 2014-07-13

    上传用户:Breathe0125