Virtex®-6 FPGA ml605 评估套件为那些需要高性能、串行连接功能和高级存储器接口的系统设计提供了开发环境。ml605 得到了预验证的参考设计和行业标准 FPGA 夹层连接器（FMC）的支持，能够利用子卡实现升级和定制。集成式工具有助于简化符合复杂设计要求的解决方案的创建。
标签： PCB fpga virtex6 ml605 pcb
上传时间： 2022-06-13
上传用户：slq1234567890
This application note covers the design considerations of a system using the performance features of the LogiCORE™ IP Advanced eXtensible Interface (AXI) Interconnect core. The design focuses on high system throughput through the AXI Interconnect core with F MAX and area optimizations in certain portions of the design. The design uses five AXI video direct memory access (VDMA) engines to simultaneously move 10 streams (five transmit video streams and five receive video streams), each in 1920 x 1080p format, 60 Hz refresh rate, and up to 32 data bits per pixel. Each VDMA is driven from a video test pattern generator (TPG) with a video timing controller (VTC) block to set up the necessary video timing signals. Data read by each AXI VDMA is sent to a common on-screen display (OSD) core capable of multiplexing or overlaying multiple video streams to a single output video stream. The output of the OSD core drives the DVI video display interface on the board. Performance monitor blocks are added to capture performance data. All 10 video streams moved by the AXI VDMA blocks are buffered through a shared DDR3 SDRAM memory and are controlled by a MicroBlaze™ processor. The reference system is targeted for the Virtex-6 XC6VLX240TFF1156-1 FPGA on the Xilinx® ml605 Rev D evaluation board
上传时间： 2013-11-14
上传用户：fdmpy
This application note covers the design considerations of a system using the performance features of the LogiCORE™ IP Advanced eXtensible Interface (AXI) Interconnect core. The design focuses on high system throughput through the AXI Interconnect core with F MAX and area optimizations in certain portions of the design. The design uses five AXI video direct memory access (VDMA) engines to simultaneously move 10 streams (five transmit video streams and five receive video streams), each in 1920 x 1080p format, 60 Hz refresh rate, and up to 32 data bits per pixel. Each VDMA is driven from a video test pattern generator (TPG) with a video timing controller (VTC) block to set up the necessary video timing signals. Data read by each AXI VDMA is sent to a common on-screen display (OSD) core capable of multiplexing or overlaying multiple video streams to a single output video stream. The output of the OSD core drives the DVI video display interface on the board. Performance monitor blocks are added to capture performance data. All 10 video streams moved by the AXI VDMA blocks are buffered through a shared DDR3 SDRAM memory and are controlled by a MicroBlaze™ processor. The reference system is targeted for the Virtex-6 XC6VLX240TFF1156-1 FPGA on the Xilinx® ml605 Rev D evaluation board
上传时间： 2013-11-23
上传用户：shen_dafa
软件无线电是一种解决无线电通信领域内多体系并存、不同体系间无法制订统一标准等问题的方案。由于软件无线电是基于软件编程实现各种功能，其主要的特点表现在灵活性和开放性上。只要在其硬件系统能处理的信号频段，想要增加相对应频段中的通信功能只需通过软件就能实现。软件无线电的特点主要体现在软件可编程和可升级上，但是不管其实现功能多样性还是频段的扩展，都必须要求硬件系统具备相应的处理能力。软件无线电硬件平台目的是为了处理信号和实现不同通信功能，在软件无线电系统中不可或缺。文章首先从理论上研究了软件无线电技术，从技术原理角度分析了软件无线电硬件平台的结构体系，比较其优缺点，最终确立了以ADI公司的AD9361射频收发芯片为核心处理器件的软件无线电硬件平台的设计方案，然后将软件无线电硬件平台分为AD9361模块、信号接口模块、电源模块这三个主要部分。其中主要介绍了AD9361芯片、信号输入/输出接口、FMC连接器、电源供电电路、电源监测电路等多个方案。在保证信号完整性和电源完整性的前提下完成了PCB版图设计。最后配合ml605开发板，对该硬件平台的各项功能进行测试，最终连接天线能够将GSM广播信号正确接收。验证了该软件无线电硬件平台设计的正确性，同时也验证了该硬件平台的功能正常，性能良好。本文设计并实现了一种基于AD936]的软件无线电硬件平台，该平台工作频率为70MHz至6GHz，包含完整的发射和接收功能，具有多种工作模式，多种应用场景的特点。通过FMC连接器与Xilinx公司的Virtex-6FPGAml605开发板相连，实现射频应用开发，在宽带通信、测试等场合均能有良好的表现，对现阶段的软件无线电研究以及产品开发有着用药的价值和意义。
上传时间： 2022-07-11
上传用户：hao123
