PCI Arbitor by VHDL
上传时间： 2013-08-18
上传用户：h886166
基于FPGA的PCI接口源代码及Testbenc
上传时间： 2013-08-19
上传用户：sun_pro12580
基于 MAXII 的CPLD 对mobil dram 的读写操作，内带源码和测试激励文件
上传时间： 2013-08-22
上传用户：luopoguixiong
基于 MAXII CPLD的对Compact_Flash的读写，擦出操作，内附测试激励文件
标签： Compact_Flash MAXII CPLD 读写
上传时间： 2013-08-22
上传用户：vodssv
基于MAXII CPLD的对1602字符型液晶进行读写操作，其中使用了一个CFI的IP核
上传时间： 2013-08-22
上传用户：yeling1919
用vhdl编写的pci源代码。花了我2000多元钱买来的，编译通过！
上传时间： 2013-08-29
上传用户：brilliantchen
PCI是一种高性能的局部总线规范，可实现各种功能标准的PCI总线卡。本文简要介绍了PCI总线的特点、信号与命令，提出了一种利用高速FPGA实现PCI总线接口的设计方案。\r\n
上传时间： 2013-08-30
上传用户：brain kung
基于FPGA的PCI总线接口的设计方案\r\n~！
上传时间： 2013-09-01
上传用户：heart520beat
PCI ExpressTM Architecture Add-in Card Compliance Checklist for the PCI Express Base 1.0a SpecificationThe PCI Special Interest Group disclaims all warranties and liability for the use of this document and the information contained herein and assumes no responsibility for any errors that may appear in this document, nor does the PCI Special Interest Group make a commitment to update the information contained herein.Contact the PCI Special Interest Group office to obtain the latest revision of this checklistQuestions regarding the ths document or membership in the PCI Special Interest Group may be forwarded tPCI Special Interest Group5440 SW Westgate Drive #217Portland, OR 97221Phone: 503-291-2569Fax: 503-297-1090 DISCLAIMERThis document is provided "as is" with no warranties whatsoever, including any warranty of merchantability, noninfringement, fitness for any particular purpose, or any warranty otherwise arising out of any proposal, specification, or sample. The PCI SIG disclaims all liability for infringement of proprietary rights, relating to use of information in this specification. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted herein.
标签： Architecture ExpressTM PCI
上传时间： 2013-11-03
上传用户：gy592333
This document provides practical, common guidelines for incorporating PCI Express interconnect layouts onto Printed Circuit Boards (PCB) ranging from 4-layer desktop baseboard designs to 10- layer or more server baseboard designs. Guidelines and constraints in this document are intended for use on both baseboard and add-in card PCB designs. This includes interconnects between PCI Express devices located on the same baseboard (chip-to-chip routing) and interconnects between a PCI Express device located “down” on the baseboard and a device located “up” on an add-in card attached through a connector. This document is intended to cover all major components of the physical interconnect including design guidelines for the PCB traces, vias and AC coupling capacitors, as well as add-in card edge-finger and connector considerations. The intent of the guidelines and examples is to help ensure that good high-speed signal design practices are used and that the timing/jitter and loss/attenuation budgets can also be met from end-to-end across the PCI Express interconnect. However, while general physical guidelines and suggestions are given, they may not necessarily guarantee adequate performance of the interconnect for all layouts and implementations. Therefore, designers should consider modeling and simulation of the interconnect in order to ensure compliance to all applicable specifications. The document is composed of two main sections. The first section provides an overview of general topology and interconnect guidelines. The second section concentrates on physical layout constraints where bulleted items at the beginning of a topic highlight important constraints, while the narrative that follows offers additional insight.
上传时间： 2013-10-15
上传用户：busterman
