tServer task executes functions at low priority (254). serverSend funtion is used to send a request to the tServer to execute a function at the tServer s priority. First tServer task executes the i() system call to print the summary of tShell task. Next an address exception is caused in tServer task by trying to execute a funtion at non-aligned word boundry. As a result SIGBUS signal is raised automatically. Signals (setjmp() and longjmp()) are used to allow the tServer task to recover gracefully from an address error exception. For more information about signals, please refer to sigLib manual pages.
标签： serverSend functions executes priority
上传时间： 2015-09-21
上传用户：tianjinfan
AutoBoot is a generic boot loader that automatically locates, loads, and executes object files from multiple types of media. AutoBoot provides a simple, fast, and functional means of loading an OS image while maintaining a small Flash memory footprint. This binary release contains a stand-alone version of AutoBoot for the DbAu1200 development board, designed to replace the YAMON boot loader.
标签： automatically AutoBoot executes generic
上传时间： 2014-01-13
上传用户：海陆空653
JMODEM executes best from a batch file as an external pro- tocol for any of the communications programs that have ex- ternal-protocol capability. A typical communications program is TELIX.
标签： communications pro executes external
上传时间： 2014-01-08
上传用户：Breathe0125
CRC码产生器与校验器程序 Features ： executes in one clock cycle per data word Any polynomial from 4 to 32 bits Any data width from 1 to 256 bits Any initialization value Synchronous or asynchronous reset
标签： polynomial Features executes clock
上传时间： 2013-12-18
上传用户：Ants
The P89LPC912/913/914 are single-chip microcontrollers in low-cost 14-pin packages, based on a high performance processor architecture that executes instructions in two to four clocks, six times the rate of standard 80C51 devices. Many system level functions have been incorporated into the P89LPC912/913/914 in order to reduce component count, board space, and system cost.
上传时间： 2013-10-11
上传用户：司令部正军级
HIGH SPEED 8051 μC CORE - Pipe-lined Instruction Architecture; executes 70% of Instructions in 1 or 2 System Clocks - Up to 25MIPS Throughput with 25MHz System Clock - 22 Vectored Interrupt Sources MEMORY - 4352 Bytes Internal Data RAM (256 + 4k) - 64k Bytes In-System Programmable FLASH Program Memory - External Parallel Data Memory Interface – up to 5Mbytes/sec DIGITAL PERIPHERALS - 64 Port I/O; All are 5V tolerant - Hardware SMBusTM (I2CTM Compatible), SPITM, and Two UART Serial Ports Available Concurrently - Programmable 16-bit Counter/Timer Array with 5 Capture/Compare Modules - 5 General Purpose 16-bit Counter/Timers - Dedicated Watch-Dog Timer; Bi-directional Reset CLOCK SOURCES - Internal Programmable Oscillator: 2-to-16MHz - External Oscillator: Crystal, RC, C, or Clock - Real-Time Clock Mode using Timer 3 or PCA SUPPLY VOLTAGE ........................ 2.7V to 3.6V - Typical Operating Current: 10mA @ 25MHz - Multiple Power Saving Sleep and Shutdown Modes 100-Pin TQFP (64-Pin Version Available) Temperature Range: –40°C to +85°C
标签： C8051F020
上传时间： 2013-10-12
上传用户：lalalal
NXP Semiconductor designed the LPC2400 microcontrollers around a 16-bit/32-bitARM7TDMI-S CPU core with real-time debug interfaces that include both JTAG andembedded Trace. The LPC2400 microcontrollers have 512 kB of on-chip high-speedFlash memory. This Flash memory includes a special 128-bit wide memory interface andaccelerator architecture that enables the CPU to execute sequential instructions fromFlash memory at the maximum 72 MHz system clock rate. This feature is available onlyon the LPC2000 ARM Microcontroller family of products. The LPC2400 can execute both32-bit ARM and 16-bit Thumb instructions. Support for the two Instruction Sets meansEngineers can choose to optimize their application for either performance or code size atthe sub-routine level. When the core executes instructions in Thumb state it can reducecode size by more than 30 % with only a small loss in performance while executinginstructions in ARM state maximizes core performance.
上传时间： 2013-11-14
上传用户：zouxinwang
Nios II 软件开发人员手册中的缓存和紧耦合存储器部分 Nios® II embedded processor cores can contain instruction and data caches. This chapter discusses cache-related issues that you need to consider to guarantee that your program executes correctly on the Nios II processor. Fortunately, most software based on the Nios II hardware abstraction layer (HAL) works correctly without any special accommodations for caches. However, some software must manage the cache directly. For code that needs direct control over the cache, the Nios II architecture provides facilities to perform the following actions:
上传时间： 2013-10-25
上传用户：虫虫虫虫虫虫
a Java program that reads a file containing instructions written in self-defined file (TPL in this case), and executes those instructions. This program should take the name of the TPL file as a command line parameter, and write its output to the console.
标签： file instructions self-defined containing
上传时间： 2015-01-10
上传用户：曹云鹏
onBlur event handler A blur event occurs when a text or textArea field on a form loses focus. The onBlur event handler executes JavaScript code when a blur event occurs. Applies to
标签： event textArea handler onBlur
上传时间： 2015-10-30
上传用户：jiahao131
