本论文来自于863项目基于光互连自组织内存服务体系(简称MemoryBox)。本文主要研究Memory Box系统中基于可重配置计算架构，软硬件携同设计方法，在XILINX VIRTEX 2 Pro FPGA上设计实现嵌入式系统。由于嵌入式系统是Memory Box工作的平台，所以硬件应具有良好的扩展性、灵活性，软件应具有优良的稳定性。在硬件平台选型时，我们选择的是基于高性能Xilinx VIRTEX2 Pro的自制开发板。嵌入式系统软硬件开发平台选用的是Xilinx EDK、ISE。内核移植所用的交叉开发工具链为powerpc-405-linux-gnu。该交叉开发工具链工作在Red Hat Enterprise LINUX．AS 4平台下。 本论文主要包括三部分工作：首先是硬件设计，其核心是EDK和ISE设计的SOPC工程；然后是嵌入式LINUX内核移植与调试；最后完成存储管理软件的设计。完全用硬件实现系统要求的各种存储管理功能极其困难。而通过移植内核，存储管理软件以运行在Linux内核上的应用软件的形式实现了其功能。存储管理软件要解决共享冲突，负载均衡，远程内存与本地内存的地址一致性以及对海量内存阵列的重新编址等问题，设计出较完善的Memory Box的存储管理模型。
上传时间： 2013-06-11
上传用户：tyler
·详细说明：DVB MHP 标准（英文版）以及 mpeg2 标准（中、英文版）-DVB MHP standard (English version) as well as mpeg2 standard (center, English version) 文件列表: DVB-MHP-spec.pdf IS138181.DOC MPEG2-0.DOC
上传时间： 2013-04-24
上传用户：sevenbestfei
·Ive been working with Windows CE for almost as long as its been in existence. A Windows programmer for many years, Im amazed by the number of different, typically quite small, systems to which I can a
上传时间： 2013-04-24
上传用户：Zxcvbnm
This application note is intended for system designers who require a hardware implementation overview of the development board features such as the power supply, the clock management, the reset control, the boot mode settings and the debug management. It shows how to use the High-density and Medium-density STM32F10xxx product families and describes the minimum hardware resources required to develop an STM32F10xxx application.
上传时间： 2013-04-24
上传用户：epson850
开关电源测试规范 说明 as
上传时间： 2013-05-22
上传用户：小鹏
采用CPLD来培植ALTERA公司的CYCLONE系列FPGA，（AS，PS，FAS）可选
上传时间： 2013-08-27
上传用户：it男一枚
This document was developed under the Standard Hardware and Reliability Program (SHARP) TechnologyIndependent Representation of Electronic Products (TIREP) project. It is intended for use by VHSIC HardwareDescription Language (VHDL) design engineers and is offered as guidance for the development of VHDL modelswhich are compliant with the VHDL Data Item Description (DID DI-EGDS-80811) and which can be providedto manufacturing engineering personnel for the development of production data and the subsequent productionof hardware. Most VHDL modeling performed to date has been concentrated at either the component level orat the conceptual system level. The assembly and sub-assembly levels have been largely disregarded. Under theSHARP TIREP project, an attempt has been made to help close this gap. The TIREP models are based upon lowcomplexity Standard Electronic Modules (SEM) of the format A configuration. Although these modules are quitesimple, it is felt that the lessons learned offer guidance which can readily be applied to a wide range of assemblytypes and complexities.
上传时间： 2014-12-23
上传用户：xinhaoshan2016
We would like to welcome you as a user of the Allegro CX, a rugged, handheld fi eld PC for data collection. Developed with the input of data collection professionals worldwide, the Allegro CX is adaptable and versatile for use in a wide variety of data collection environments. The Allegro CX continues to utilize our ergonomic, lightweight design that is standard in our line of Allegro Field PCs. This design makes your Allegro easy to use for extended periods while moving to and from data collection sites in the fi eld.
上传时间： 2014-12-23
上传用户：gaojiao1999
本文简单讨论并总结了VHDL、Verilog，System verilog 这三中语言的各自特点和区别As the number of enhancements to variousHardware Description Languages (HDLs) hasincreased over the past year, so too has the complexityof determining which language is best fora particular design. Many designers and organizationsare contemplating whether they shouldswitch from one HDL to another.
标签： Verilog verilog System VHDL
上传时间： 2013-10-16
上传用户：牛布牛
Abstract: This document explains how the Cupertino (MAXREFDES5#) subsystem reference design meets the higher resolution, higher voltage,and isolation needs of industrial control and industrial automation applications. Hardware and firmware design files as well as FFTs andhistograms from lab measurements are provided.
上传时间： 2013-10-21
上传用户：mnacyf
